Lines Matching refs:ARRAY_SIZE

141 		HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
145 HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
149 HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
154 HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
159 HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
164 HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
169 HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
174 HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
179 HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p),
514 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
519 ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
522 ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
527 ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
540 ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
543 ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
546 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
557 ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
559 ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
561 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
599 ARRAY_SIZE(shub_source_clk_mux_p),
605 shub_uart_source_clk_mux_p, ARRAY_SIZE(shub_uart_source_clk_mux_p),
710 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
715 ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
720 ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
725 ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
738 ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
741 ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
744 ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
747 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
758 ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
760 ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
762 ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
764 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);