drivers/clk/clk-versaclock5.c

172 	u32			div_int;
435 	u32 div_int, div_frc;
440 	div_int = (fb[0] << 4) | (fb[1] >> 4);
444 	return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
452 	u32 div_int;
458 	div_int = rate / *parent_rate;
459 	if (div_int > 0xfff)
467 	hwdata->div_int = div_int;
470 	return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
480 	fb[0] = hwdata->div_int >> 4;
481 	fb[1] = hwdata->div_int << 4;
502 	u32 div_int, div_frc;
511 	div_int = (od_int[0] << 4) | (od_int[1] >> 4);
516 	if (div_int == 0 && div_frc == 0)
520 	return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
529 	u32 div_int;
533 	div_int = f_in / rate;
539 	if (div_int > 0xffe) {
540 		div_int = 0xffe;
541 		rate = f_in / div_int;
549 	hwdata->div_int = div_int;
552 	return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
565 		hwdata->div_int >> 4, hwdata->div_int << 4,