drivers/clk/clk-versaclock3.c

139 	u8 offs;
145 	u8 offs;
160 	u8 offs;
219 	regmap_read(vc3->regmap, pfd_mux->offs, &src);
229 	return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk,
248 	regmap_read(vc3->regmap, pfd->offs, &prediv);
323 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
325 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0);
332 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk,
334 		regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
343 		regmap_write(vc3->regmap, pfd->offs, div);
448 	regmap_read(vc3->regmap, div_mux->offs, &src);
458 	return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk,
487 	regmap_read(vc3->regmap, div_data->offs, &val);
504 		regmap_read(vc3->regmap, div_data->offs, &bestdiv);
524 	return regmap_update_bits(vc3->regmap, div_data->offs,
560 	regmap_read(vc3->regmap, clk_mux->offs, &val);
570 	return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk,
597 			.offs = VC3_PLL_OP_CTRL,
610 			.offs = VC3_GENERAL_CTR,
627 			.offs = VC3_PLL1_M_DIVIDER,
644 			.offs = VC3_PLL2_M_DIVIDER,
661 			.offs = VC3_PLL3_M_DIVIDER,
752 			.offs = VC3_GENERAL_CTR,
765 			.offs = VC3_PLL3_CHARGE_PUMP_CTRL,
778 			.offs = VC3_OUTPUT_CTR,
794 			.offs = VC3_OUT_DIV1_DIV2_CTRL,
812 			.offs = VC3_OUT_DIV1_DIV2_CTRL,
830 			.offs = VC3_OUT_DIV3_DIV4_CTRL,
848 			.offs = VC3_OUT_DIV3_DIV4_CTRL,
866 			.offs = VC3_PLL1_CTRL_OUTDIV5,
887 			.offs = VC3_SE1_DIV4_CTRL,
903 			.offs = VC3_SE2_CTRL_REG0,
919 			.offs = VC3_SE3_DIFF1_CTRL_REG,
935 			.offs = VC3_DIFF1_CTRL_REG,
951 			.offs = VC3_DIFF2_CTRL_REG,