Lines Matching refs:hws
53 static struct clk_hw **hws;
513 hws[SYS_D1CPRE] = clk_hw_register_divider_table(NULL, "d1cpre",
517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",
523 hws[CPU_SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick",
527 hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0,
533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0,
542 hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0,
551 hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0,
1203 clk_data = kzalloc(struct_size(clk_data, hws, STM32H7_MAX_CLKS),
1210 hws = clk_data->hws;
1213 hws[n] = ERR_PTR(-ENOENT);
1247 hws[CK_DSI_PHY] = clk_hw_register_fixed_rate(NULL, "ck_dsi_phy", NULL,
1250 hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
1254 hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
1261 hws[MCLK_BANK + n] = clk_hw_register_mux(NULL,
1276 hws[OSC_BANK + n] = clk_register_ready_gate(NULL,
1285 hws[HSE_CK] = clk_register_ready_gate(NULL,
1293 hws[LSE_CK] = clk_register_ready_gate(NULL,
1301 hws[CSI_KER_DIV122 + n] = clk_hw_register_fixed_factor(NULL,
1321 hws[ODF_BANK + idx] = clk_hw_register_composite(NULL,
1334 hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
1344 hws[KERN_BANK + n] = clk_hw_register_composite(NULL,
1359 hws[RTC_CK] = clk_hw_register_composite(NULL,
1373 hws[MCO_BANK + n] = clk_hw_register_composite(NULL,