drivers/clk/clk-cdce925.c

54 	u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
274 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
280 			0x03, (pdiv >> 8) & 0x03);
281 		regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
284 		regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
287 		regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
290 		regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
293 		regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
296 		regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
299 		regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
302 		regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
305 		regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
340 	cdce925_clk_set_pdiv(data, data->pdiv);
358 	if (data->pdiv)
359 		return parent_rate / data->pdiv;
445 	data->pdiv = cdce925_calc_divider(rate, parent_rate);
492 	data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
731 	data->clk[0].pdiv = 1;
753 		data->clk[i].pdiv = 1;