Lines Matching defs:divider
20 * input pll and divider. The virtual structure as it is used in Marvell
35 * (C) programmable clock divider controlled by <Select[1:n]>
36 * (D) constant div-by-3 clock divider
37 * (E) programmable clock divider bypass controlled by <Switch>
181 u32 divsw, div3sw, divider = 1;
193 divider = 3;
194 /* divider can be bypassed with DIV_SWITCH == 0 */
196 divider = 1;
197 /* clock divider determined by DIV_SELECT */
203 divider = clk_div[reg];
209 return parent_rate / divider;