Lines Matching refs:reg
33 * reg should be an u32 variable.
36 #define PLL_REG_GET_LOW(reg) \
37 (((reg) & (0x3F << 0)) >> 0)
38 #define PLL_REG_GET_HIGH(reg) \
39 (((reg) & (0x3F << 6)) >> 6)
40 #define PLL_REG_GET_EDGE(reg) \
41 (((reg) & (BIT(12))) ? 1 : 0)
42 #define PLL_REG_GET_BYPASS(reg) \
43 (((reg) & (BIT(13))) ? 1 : 0)
44 #define PLL_REG_GET_NOUPD(reg) \
45 (((reg) & (BIT(14))) ? 1 : 0)
46 #define PLL_REG_GET_PAD(reg) \
47 (((reg) & (0x1FFFF << 15)) >> 15)
49 #define PLL_REG_SET_LOW(reg, value) \
50 { reg |= (((value) & 0x3F) << 0); }
51 #define PLL_REG_SET_HIGH(reg, value) \
52 { reg |= (((value) & 0x3F) << 6); }
53 #define PLL_REG_SET_EDGE(reg, value) \
54 { reg |= (((value) & 0x01) << 12); }
55 #define PLL_REG_SET_BYPASS(reg, value) \
56 { reg |= (((value) & 0x01) << 13); }
57 #define PLL_REG_SET_NOUPD(reg, value) \
58 { reg |= (((value) & 0x01) << 14); }
59 #define PLL_REG_SET_PAD(reg, value) \
60 { reg |= (((value) & 0x1FFFF) << 15); }
98 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
101 iowrite32(val, clk->base + reg);
104 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
106 return ioread32(clk->base + reg);
114 static inline u32 axs10x_div_get_value(u32 reg)
116 if (PLL_REG_GET_BYPASS(reg))
119 return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);