clk/axs10x/i2s_pll_clock.c

115 	const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
118 	if (!pll_cfg) {
123 	for (i = 0; pll_cfg[i].rate != 0; i++)
124 		if (pll_cfg[i].rate == rate)
134 	const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(parent_rate);
137 	if (!pll_cfg) {
142 	for (i = 0; pll_cfg[i].rate != 0; i++) {
143 		if (pll_cfg[i].rate == rate) {
144 			i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv);
145 			i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv);
146 			i2s_pll_write(clk, PLL_ODIV0_REG, pll_cfg[i].odiv0);
147 			i2s_pll_write(clk, PLL_ODIV1_REG, pll_cfg[i].odiv1);