clk/at91/clk-master.c

46 static inline bool clk_master_ready(struct clk_master *master)
48 	unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
51 	regmap_read(master->regmap, AT91_PMC_SR, &status);
58 	struct clk_master *master = to_clk_master(hw);
61 	spin_lock_irqsave(master->lock, flags);
63 	while (!clk_master_ready(master))
66 	spin_unlock_irqrestore(master->lock, flags);
73 	struct clk_master *master = to_clk_master(hw);
77 	spin_lock_irqsave(master->lock, flags);
78 	status = clk_master_ready(master);
79 	spin_unlock_irqrestore(master->lock, flags);
89 	struct clk_master *master = to_clk_master(hw);
90 	const struct clk_master_layout *layout = master->layout;
92 						master->characteristics;
95 	spin_lock_irqsave(master->lock, flags);
96 	regmap_read(master->regmap, master->layout->offset, &mckr);
97 	spin_unlock_irqrestore(master->lock, flags);
106 		pr_warn("master clk div is underclocked");
108 		pr_warn("master clk div is overclocked");
115 	struct clk_master *master = to_clk_master(hw);
120 	spin_lock_irqsave(master->lock, flags);
121 	regmap_read(master->regmap, master->layout->offset, &mckr);
122 	spin_unlock_irqrestore(master->lock, flags);
124 	mckr &= master->layout->mask;
126 	div = master->characteristics->divisors[div];
128 	master->pms.parent_rate = clk_hw_get_rate(parent_hw);
129 	master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);
136 	struct clk_master *master = to_clk_master(hw);
141 	spin_lock_irqsave(master->lock, flags);
142 	regmap_read(master->regmap, master->layout->offset, &mckr);
143 	spin_unlock_irqrestore(master->lock, flags);
145 	mckr &= master->layout->mask;
147 	div = master->characteristics->divisors[div];
149 	if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))
162 static int clk_master_div_set(struct clk_master *master,
166 						master->characteristics;
188 	ret = regmap_read(master->regmap, master->layout->offset, &mckr);
192 	mckr &= master->layout->mask;
199 		pr_warn("master clk div is underclocked");
201 		pr_warn("master clk div is overclocked");
205 	ret = regmap_write(master->regmap, master->layout->offset, mckr);
209 	while (!clk_master_ready(master))
212 	master->div = characteristics->divisors[div_index];
220 	struct clk_master *master = to_clk_master(hw);
222 	return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
227 	struct clk_master *master = to_clk_master(hw);
231 	spin_lock_irqsave(master->lock, flags);
232 	ret = clk_master_div_set(master, master->pms.parent_rate,
233 				 DIV_ROUND_CLOSEST(master->pms.parent_rate,
234 						   master->pms.rate));
235 	spin_unlock_irqrestore(master->lock, flags);
380 	struct clk_master *master = to_clk_master(hw);
382 						master->characteristics;
386 	spin_lock_irqsave(master->lock, flags);
387 	regmap_read(master->regmap, master->layout->offset, &val);
388 	spin_unlock_irqrestore(master->lock, flags);
390 	val &= master->layout->mask;
391 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
402 	struct clk_master *master = to_clk_master(hw);
406 	spin_lock_irqsave(master->lock, flags);
407 	regmap_read(master->regmap, master->layout->offset, &mckr);
408 	spin_unlock_irqrestore(master->lock, flags);
410 	mckr &= master->layout->mask;
417 	struct clk_master *master = to_clk_master(hw);
422 	spin_lock_irqsave(master->lock, flags);
423 	regmap_read(master->regmap, master->layout->offset, &val);
424 	spin_unlock_irqrestore(master->lock, flags);
426 	val &= master->layout->mask;
427 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
428 	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
433 	master->pms.parent = val & AT91_PMC_CSS;
434 	master->pms.parent_rate = clk_hw_get_rate(parent_hw);
435 	master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);
442 	struct clk_master *master = to_clk_master(hw);
446 	spin_lock_irqsave(master->lock, flags);
447 	regmap_read(master->regmap, master->layout->offset, &val);
448 	spin_unlock_irqrestore(master->lock, flags);
450 	val &= master->layout->mask;
451 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
452 	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
457 	if (master->pms.rate !=
458 	    DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||
459 	    (master->pms.parent != (val & AT91_PMC_CSS)))
481 	struct clk_master *master;
491 	master = kzalloc(sizeof(*master), GFP_KERNEL);
492 	if (!master)
504 	master->hw.init = &init;
505 	master->layout = layout;
506 	master->characteristics = characteristics;
507 	master->regmap = regmap;
508 	master->lock = lock;
511 		spin_lock_irqsave(master->lock, irqflags);
512 		regmap_read(master->regmap, master->layout->offset, &mckr);
513 		spin_unlock_irqrestore(master->lock, irqflags);
517 		master->div = characteristics->divisors[mckr];
520 	hw = &master->hw;
521 	ret = clk_hw_register(NULL, &master->hw);
523 		kfree(master);
581 	struct clk_master *master = to_clk_master(hw);
583 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
589 	struct clk_master *master = to_clk_master(hw);
618 	if (master->chg_pid < 0)
621 	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);
661 	struct clk_master *master = to_clk_master(hw);
665 	spin_lock_irqsave(master->lock, flags);
666 	index = clk_mux_val_to_index(&master->hw, master->mux_table, 0,
667 				     master->parent);
668 	spin_unlock_irqrestore(master->lock, flags);
675 	struct clk_master *master = to_clk_master(hw);
681 	spin_lock_irqsave(master->lock, flags);
682 	master->parent = clk_mux_index_to_val(master->mux_table, 0, index);
683 	spin_unlock_irqrestore(master->lock, flags);
688 static void clk_sama7g5_master_set(struct clk_master *master,
694 	unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;
695 	unsigned int div = master->div << MASTER_DIV_SHIFT;
697 	spin_lock_irqsave(master->lock, flags);
699 	regmap_write(master->regmap, AT91_PMC_MCR_V2,
700 		     AT91_PMC_MCR_V2_ID(master->id));
701 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
702 	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
706 			   AT91_PMC_MCR_V2_ID(master->id));
711 	while ((cparent != master->parent) && !clk_master_ready(master))
714 	spin_unlock_irqrestore(master->lock, flags);
719 	struct clk_master *master = to_clk_master(hw);
721 	clk_sama7g5_master_set(master, 1);
728 	struct clk_master *master = to_clk_master(hw);
731 	spin_lock_irqsave(master->lock, flags);
733 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
734 	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
738 			   AT91_PMC_MCR_V2_ID(master->id));
740 	spin_unlock_irqrestore(master->lock, flags);
745 	struct clk_master *master = to_clk_master(hw);
749 	spin_lock_irqsave(master->lock, flags);
751 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
752 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
754 	spin_unlock_irqrestore(master->lock, flags);
762 	struct clk_master *master = to_clk_master(hw);
774 	spin_lock_irqsave(master->lock, flags);
775 	master->div = div;
776 	spin_unlock_irqrestore(master->lock, flags);
783 	struct clk_master *master = to_clk_master(hw);
785 	master->pms.status = clk_sama7g5_master_is_enabled(hw);
792 	struct clk_master *master = to_clk_master(hw);
794 	if (master->pms.status)
795 		clk_sama7g5_master_set(master, master->pms.status);
820 	struct clk_master *master;
831 	master = kzalloc(sizeof(*master), GFP_KERNEL);
832 	if (!master)
848 	master->hw.init = &init;
849 	master->regmap = regmap;
850 	master->id = id;
851 	master->chg_pid = chg_pid;
852 	master->lock = lock;
853 	master->mux_table = mux_table;
855 	spin_lock_irqsave(master->lock, flags);
856 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
857 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
858 	master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
859 	master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
860 	spin_unlock_irqrestore(master->lock, flags);
862 	hw = &master->hw;
863 	ret = clk_hw_register(NULL, &master->hw);
865 		kfree(master);