Lines Matching refs:property
97 u32 property, ranges[4];
148 * CS# from the reg property instead.
150 err = of_property_read_u32(child, "reg", &property);
153 "failed to decode CS: no reg property found\n");
157 property = ranges[1];
161 if (property >= TEGRA_GMI_MAX_CHIP_SELECT) {
162 dev_err(gmi->dev, "invalid chip select: %d", property);
167 gmi->snor_config |= TEGRA_GMI_CS_SELECT(property);
170 if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
171 gmi->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
175 if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
176 gmi->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
180 if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
181 gmi->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
185 if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
186 gmi->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
190 if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
191 gmi->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
195 if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
196 gmi->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
200 if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
201 gmi->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);