mhi/ep/mmio.c

13 u32 mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset)
15 	return readl(mhi_cntrl->mmio + offset);
18 void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val)
20 	writel(val, mhi_cntrl->mmio + offset);
23 void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val)
27 	regval = mhi_ep_mmio_read(mhi_cntrl, offset);
30 	mhi_ep_mmio_write(mhi_cntrl, offset, regval);
44 void mhi_ep_mmio_get_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state *state,
49 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICTRL);
54 static void mhi_ep_mmio_set_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id, bool enable)
64 	mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CHDB_INT_MASK_n(chdb_idx), chid_mask, val);
67 	mhi_cntrl->chdb[chdb_idx].mask &= ~chid_mask;
68 	mhi_cntrl->chdb[chdb_idx].mask |= val << chid_shift;
71 void mhi_ep_mmio_enable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
73 	mhi_ep_mmio_set_chdb(mhi_cntrl, ch_id, true);
76 void mhi_ep_mmio_disable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
78 	mhi_ep_mmio_set_chdb(mhi_cntrl, ch_id, false);
81 static void mhi_ep_mmio_set_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable)
88 		mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_MASK_n(i), val);
89 		mhi_cntrl->chdb[i].mask = val;
93 void mhi_ep_mmio_enable_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
95 	mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, true);
98 static void mhi_ep_mmio_mask_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
100 	mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, false);
103 bool mhi_ep_mmio_read_chdb_status_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
109 		mhi_cntrl->chdb[i].status = mhi_ep_mmio_read(mhi_cntrl, MHI_CHDB_INT_STATUS_n(i));
110 		if (mhi_cntrl->chdb[i].status)
118 static void mhi_ep_mmio_set_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable)
125 		mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_MASK_n(i), val);
128 static void mhi_ep_mmio_mask_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
130 	mhi_ep_mmio_set_erdb_interrupts(mhi_cntrl, false);
133 void mhi_ep_mmio_enable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
135 	mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
139 void mhi_ep_mmio_disable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
141 	mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
145 void mhi_ep_mmio_enable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
147 	mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
151 void mhi_ep_mmio_disable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
153 	mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
157 void mhi_ep_mmio_mask_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
159 	mhi_ep_mmio_disable_ctrl_interrupt(mhi_cntrl);
160 	mhi_ep_mmio_disable_cmdb_interrupt(mhi_cntrl);
161 	mhi_ep_mmio_mask_chdb_interrupts(mhi_cntrl);
162 	mhi_ep_mmio_mask_erdb_interrupts(mhi_cntrl);
165 static void mhi_ep_mmio_clear_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
170 		mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_CLEAR_n(i),
174 		mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_CLEAR_n(i),
177 	mhi_ep_mmio_write(mhi_cntrl, MHI_CTRL_INT_CLEAR,
183 void mhi_ep_mmio_get_chc_base(struct mhi_ep_cntrl *mhi_cntrl)
187 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_HIGHER);
188 	mhi_cntrl->ch_ctx_host_pa = regval;
189 	mhi_cntrl->ch_ctx_host_pa <<= 32;
191 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_LOWER);
192 	mhi_cntrl->ch_ctx_host_pa |= regval;
195 void mhi_ep_mmio_get_erc_base(struct mhi_ep_cntrl *mhi_cntrl)
199 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_HIGHER);
200 	mhi_cntrl->ev_ctx_host_pa = regval;
201 	mhi_cntrl->ev_ctx_host_pa <<= 32;
203 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_LOWER);
204 	mhi_cntrl->ev_ctx_host_pa |= regval;
207 void mhi_ep_mmio_get_crc_base(struct mhi_ep_cntrl *mhi_cntrl)
211 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_HIGHER);
212 	mhi_cntrl->cmd_ctx_host_pa = regval;
213 	mhi_cntrl->cmd_ctx_host_pa <<= 32;
215 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_LOWER);
216 	mhi_cntrl->cmd_ctx_host_pa |= regval;
221 	struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl;
225 	regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h);
229 	regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l);
235 void mhi_ep_mmio_set_env(struct mhi_ep_cntrl *mhi_cntrl, u32 value)
237 	mhi_ep_mmio_write(mhi_cntrl, EP_BHI_EXECENV, value);
240 void mhi_ep_mmio_clear_reset(struct mhi_ep_cntrl *mhi_cntrl)
242 	mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHICTRL, MHICTRL_RESET_MASK, 0);
245 void mhi_ep_mmio_reset(struct mhi_ep_cntrl *mhi_cntrl)
247 	mhi_ep_mmio_write(mhi_cntrl, EP_MHICTRL, 0);
248 	mhi_ep_mmio_write(mhi_cntrl, EP_MHISTATUS, 0);
249 	mhi_ep_mmio_clear_interrupts(mhi_cntrl);
252 void mhi_ep_mmio_init(struct mhi_ep_cntrl *mhi_cntrl)
256 	mhi_cntrl->chdb_offset = mhi_ep_mmio_read(mhi_cntrl, EP_CHDBOFF);
257 	mhi_cntrl->erdb_offset = mhi_ep_mmio_read(mhi_cntrl, EP_ERDBOFF);
259 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
260 	mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
261 	mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);
263 	mhi_ep_mmio_reset(mhi_cntrl);
266 void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl)
270 	regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
271 	mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
272 	mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);