drivers/atm/he.c

176 #define he_writel(dev, val, reg)	do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
185 	he_writel(he_dev, val, CON_DAT);
187 	he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
203 	he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
455 	he_writel(he_dev, lbufd_index, RLBF0_H);
471 	he_writel(he_dev, lbufd_index - 2, RLBF0_T);
472 	he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
485 	he_writel(he_dev, lbufd_index, RLBF1_H);
501 	he_writel(he_dev, lbufd_index - 2, RLBF1_T);
502 	he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
515 	he_writel(he_dev, lbufd_index, TLBF_H);
531 	he_writel(he_dev, lbufd_index - 1, TLBF_T);
548 	he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
549 	he_writel(he_dev, 0, TPDRQ_T);
550 	he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
776 	he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
777 	he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
778 	he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
779 	he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
832 	he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
833 	he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
835 	he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
837 	he_writel(he_dev,
854 	he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
855 	he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
856 	he_writel(he_dev,
861 		he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
864 		he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
879 	he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
880 	he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
881 	he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
882 	he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
930 	he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
931 	he_writel(he_dev,
934 	he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
935 	he_writel(he_dev, 0x0, IRQ0_DATA);
937 	he_writel(he_dev, 0x0, IRQ1_BASE);
938 	he_writel(he_dev, 0x0, IRQ1_HEAD);
939 	he_writel(he_dev, 0x0, IRQ1_CNTL);
940 	he_writel(he_dev, 0x0, IRQ1_DATA);
942 	he_writel(he_dev, 0x0, IRQ2_BASE);
943 	he_writel(he_dev, 0x0, IRQ2_HEAD);
944 	he_writel(he_dev, 0x0, IRQ2_CNTL);
945 	he_writel(he_dev, 0x0, IRQ2_DATA);
947 	he_writel(he_dev, 0x0, IRQ3_BASE);
948 	he_writel(he_dev, 0x0, IRQ3_HEAD);
949 	he_writel(he_dev, 0x0, IRQ3_CNTL);
950 	he_writel(he_dev, 0x0, IRQ3_DATA);
954 	he_writel(he_dev, 0x0, GRP_10_MAP);
955 	he_writel(he_dev, 0x0, GRP_32_MAP);
956 	he_writel(he_dev, 0x0, GRP_54_MAP);
957 	he_writel(he_dev, 0x0, GRP_76_MAP);
1054 	he_writel(he_dev, 0x0, RESET_CNTL);
1055 	he_writel(he_dev, 0xff, RESET_CNTL);
1107 	he_writel(he_dev, lb_swap, LB_SWAP);
1110 	he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
1114 	he_writel(he_dev, lb_swap, LB_SWAP);
1123 	he_writel(he_dev, host_cntl, HOST_CNTL);
1221 	he_writel(he_dev,
1228 	he_writel(he_dev, BANK_ON |
1232 	he_writel(he_dev,
1235 	he_writel(he_dev,
1239 	he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
1241 	he_writel(he_dev,
1247 	he_writel(he_dev, DRF_THRESH(0x20) |
1252 	he_writel(he_dev, 0x0, TXAAL5_PROTO);
1254 	he_writel(he_dev, PHY_INT_ENB |
1297 	he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
1298 	he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
1299 	he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
1300 	he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
1301 	he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
1331 	he_writel(he_dev, 0x08000, RCMLBM_BA);
1332 	he_writel(he_dev, 0x0e000, RCMRSRB_BA);
1333 	he_writel(he_dev, 0x0d800, RCMABR_BA);
1340 	he_writel(he_dev, 0x0, RLBC_H);
1341 	he_writel(he_dev, 0x0, RLBC_T);
1342 	he_writel(he_dev, 0x0, RLBC_H2);
1344 	he_writel(he_dev, 512, RXTHRSH);	/* 10% of r0+r1 buffers */
1345 	he_writel(he_dev, 256, LITHRSH); 	/* 5% of r0+r1 buffers */
1349 	he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
1354 		he_writel(he_dev, 0x000f, G0_INMQ_S);
1355 		he_writel(he_dev, 0x200f, G0_INMQ_L);
1357 		he_writel(he_dev, 0x001f, G1_INMQ_S);
1358 		he_writel(he_dev, 0x201f, G1_INMQ_L);
1360 		he_writel(he_dev, 0x002f, G2_INMQ_S);
1361 		he_writel(he_dev, 0x202f, G2_INMQ_L);
1363 		he_writel(he_dev, 0x003f, G3_INMQ_S);
1364 		he_writel(he_dev, 0x203f, G3_INMQ_L);
1366 		he_writel(he_dev, 0x004f, G4_INMQ_S);
1367 		he_writel(he_dev, 0x204f, G4_INMQ_L);
1369 		he_writel(he_dev, 0x005f, G5_INMQ_S);
1370 		he_writel(he_dev, 0x205f, G5_INMQ_L);
1372 		he_writel(he_dev, 0x006f, G6_INMQ_S);
1373 		he_writel(he_dev, 0x206f, G6_INMQ_L);
1375 		he_writel(he_dev, 0x007f, G7_INMQ_S);
1376 		he_writel(he_dev, 0x207f, G7_INMQ_L);
1378 		he_writel(he_dev, 0x0000, G0_INMQ_S);
1379 		he_writel(he_dev, 0x0008, G0_INMQ_L);
1381 		he_writel(he_dev, 0x0001, G1_INMQ_S);
1382 		he_writel(he_dev, 0x0009, G1_INMQ_L);
1384 		he_writel(he_dev, 0x0002, G2_INMQ_S);
1385 		he_writel(he_dev, 0x000a, G2_INMQ_L);
1387 		he_writel(he_dev, 0x0003, G3_INMQ_S);
1388 		he_writel(he_dev, 0x000b, G3_INMQ_L);
1390 		he_writel(he_dev, 0x0004, G4_INMQ_S);
1391 		he_writel(he_dev, 0x000c, G4_INMQ_L);
1393 		he_writel(he_dev, 0x0005, G5_INMQ_S);
1394 		he_writel(he_dev, 0x000d, G5_INMQ_L);
1396 		he_writel(he_dev, 0x0006, G6_INMQ_S);
1397 		he_writel(he_dev, 0x000e, G6_INMQ_L);
1399 		he_writel(he_dev, 0x0007, G7_INMQ_S);
1400 		he_writel(he_dev, 0x000f, G7_INMQ_L);
1405 	he_writel(he_dev, 0x0, MCC);
1406 	he_writel(he_dev, 0x0, OEC);
1407 	he_writel(he_dev, 0x0, DCC);
1408 	he_writel(he_dev, 0x0, CEC);
1436 		he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
1437 		he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
1438 		he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
1439 		he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1442 		he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
1443 		he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
1444 		he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1446 		he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
1448 		he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
1449 		he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
1450 		he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1452 		he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
1454 		he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
1455 		he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
1456 		he_writel(he_dev, TBRQ_THRESH(0x1),
1458 		he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
1470 	he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
1499 	he_writel(he_dev, reg, RC_CONFIG);
1550 		he_writel(he_dev, reg, RC_CONFIG);
1791 		he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
1872 		he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
1921 		he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
2002 		he_writel(he_dev,
2041 		he_writel(he_dev, INT_CLEAR_A, INT_FIFO);	/* clear interrupt */
2110 	he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
2678 	he_writel(he_dev, val, FRAMER + (addr*4));
2795 	he_writel(he_dev, val, HOST_CNTL);
2799 		he_writel(he_dev, val | readtab[i], HOST_CNTL);
2805 		he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2807 		he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2814 	he_writel(he_dev, val, HOST_CNTL);
2818 		he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2823 		he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2827 	he_writel(he_dev, val | ID_CS, HOST_CNTL);