drivers/ata/sata_mv.c

832 	(void) readl(addr);	/* flush to avoid PCI posted write */
920 	pp->cached.fiscfg = readl(port_mmio + FISCFG);
921 	pp->cached.ltmode = readl(port_mmio + LTMODE);
922 	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
923 	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
1170 		u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1194 		u32 reg = readl(port_mmio + EDMA_CMD);
1228 				       "%08x ", readl(start + b));
1315 		*val = readl(mv_ap_base(link->ap) + ofs);
1342 			if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1478 	old = readl(hpriv->base + GPIO_PORT_CTL);
1536 	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1562 	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1900 	cmd = readl(port_mmio + BMDMA_CMD);
1933 	reg = readl(port_mmio + BMDMA_STATUS);
2200 	old_ifctl = readl(port_mmio + SATA_IFCTL);
2217 		ifstat = readl(port_mmio + SATA_IFSTAT);
2431 	return readl(port_mmio + SATA_TESTCTL) >> 16;
2462 	in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2464 	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2622 	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2624 		fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2775 	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2923 	err_cause = readl(mmio + hpriv->irq_cause_offset);
2982 	main_irq_cause = readl(hpriv->main_irq_cause_addr);
3029 		*val = readl(addr + ofs);
3057 		u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3076 	tmp = readl(phy_mmio + MV5_PHY_MODE);
3090 	tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3104 		tmp = readl(phy_mmio + MV5_LTMODE);
3108 		tmp = readl(phy_mmio + MV5_PHY_CTL);
3114 	tmp = readl(phy_mmio + MV5_PHY_MODE);
3159 	tmp = readl(hc_mmio + 0x20);
3190 	tmp = readl(mmio + MV_PCI_MODE);
3213 	tmp = readl(mmio + GPIO_PORT_CTL);
3238 	t = readl(reg);
3243 		t = readl(reg);
3257 		t = readl(reg);
3271 		t = readl(reg);
3289 	tmp = readl(mmio + RESET_CFG);
3297 	tmp = readl(port_mmio + PHY_MODE2);
3321 		m2 = readl(port_mmio + PHY_MODE2);
3328 		m2 = readl(port_mmio + PHY_MODE2);
3339 	m3 = readl(port_mmio + PHY_MODE3);
3347 		u32 m4 = readl(port_mmio + PHY_MODE4);
3368 	m2 = readl(port_mmio + PHY_MODE2);
3399 	tmp = readl(port_mmio + PHY_MODE2);
3476 	reg = readl(port_mmio + PHY_MODE3);
3483 	reg = readl(port_mmio + PHY_MODE4);
3488 	reg = readl(port_mmio + PHY_MODE9_GEN2);
3494 	reg = readl(port_mmio + PHY_MODE9_GEN1);
3512 	if (readl(port0_mmio + PHYCFG_OFS))
3519 	u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3563 		u32 reg = readl(port_mmio + SATA_IFCTL);
3685 	writelfl(readl(serr), serr);
3700 	reg = readl(mmio + MV_PCI_MODE);
3713 		reg = readl(mmio + MV_PCI_COMMAND);
3727 		u32 reg = readl(mmio + MV_PCI_COMMAND);
3905 	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3936 			readl(hc_mmio + HC_CFG),
3937 			readl(hc_mmio + HC_IRQ_CAUSE));