drivers/ata/sata_gemini.c

125 bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1)
127 	if (!sg->sata_bridge)
133 	if ((sg->muxmode == GEMINI_MUXMODE_2) &&
136 	if ((sg->muxmode == GEMINI_MUXMODE_3) &&
144 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg)
146 	return sg->muxmode;
150 static int gemini_sata_setup_bridge(struct sata_gemini *sg,
160 		if (sg->muxmode == GEMINI_MUXMODE_2)
162 		writel(val, sg->base + GEMINI_SATA0_CTRL);
166 		if (sg->muxmode == GEMINI_MUXMODE_3)
168 		writel(val, sg->base + GEMINI_SATA1_CTRL);
179 			val = readl(sg->base + GEMINI_SATA0_STATUS);
181 			val = readl(sg->base + GEMINI_SATA1_STATUS);
188 	dev_info(sg->dev, "SATA%d PHY %s\n", bridge,
194 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
200 		pclk = sg->sata0_pclk;
202 		pclk = sg->sata1_pclk;
210 	ret = gemini_sata_setup_bridge(sg, bridge);
218 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
221 		clk_disable(sg->sata0_pclk);
223 		clk_disable(sg->sata1_pclk);
227 int gemini_sata_reset_bridge(struct sata_gemini *sg,
231 		reset_control_reset(sg->sata0_reset);
233 		reset_control_reset(sg->sata1_reset);
235 	return gemini_sata_setup_bridge(sg, bridge);
239 static int gemini_sata_bridge_init(struct sata_gemini *sg)
241 	struct device *dev = sg->dev;
245 	sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK");
246 	if (IS_ERR(sg->sata0_pclk)) {
250 	sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK");
251 	if (IS_ERR(sg->sata1_pclk)) {
256 	ret = clk_prepare_enable(sg->sata0_pclk);
261 	ret = clk_prepare_enable(sg->sata1_pclk);
264 		clk_disable_unprepare(sg->sata0_pclk);
268 	sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
269 	if (IS_ERR(sg->sata0_reset)) {
271 		clk_disable_unprepare(sg->sata1_pclk);
272 		clk_disable_unprepare(sg->sata0_pclk);
273 		return PTR_ERR(sg->sata0_reset);
275 	sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
276 	if (IS_ERR(sg->sata1_reset)) {
278 		clk_disable_unprepare(sg->sata1_pclk);
279 		clk_disable_unprepare(sg->sata0_pclk);
280 		return PTR_ERR(sg->sata1_reset);
283 	sata_id = readl(sg->base + GEMINI_SATA_ID);
284 	sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
285 	sg->sata_bridge = true;
286 	clk_disable(sg->sata0_pclk);
287 	clk_disable(sg->sata1_pclk);
321 	struct sata_gemini *sg;
328 	sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
329 	if (!sg)
331 	sg->dev = dev;
333 	sg->base = devm_platform_ioremap_resource(pdev, 0);
334 	if (IS_ERR(sg->base))
335 		return PTR_ERR(sg->base);
345 		ret = gemini_sata_bridge_init(sg);
351 		sg->ide_pins = true;
353 	if (!sg->sata_bridge && !sg->ide_pins) {
369 	sg->muxmode = muxmode;
385 	if (sg->ide_pins) {
392 	platform_set_drvdata(pdev, sg);
393 	sg_singleton = sg;
398 	if (sg->sata_bridge) {
399 		clk_unprepare(sg->sata1_pclk);
400 		clk_unprepare(sg->sata0_pclk);
407 	struct sata_gemini *sg = platform_get_drvdata(pdev);
409 	if (sg->sata_bridge) {
410 		clk_unprepare(sg->sata1_pclk);
411 		clk_unprepare(sg->sata0_pclk);