Lines Matching defs:timing
48 * timing and policy set up. Each HDD in raid mode also has a serial
92 The high byte is the 66Mhz timing */
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 * Program the PIO/MWDMA timing for this channel according to the
126 static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
133 /* Program PIO/MWDMA timing bits */
135 conf = timing >> 8;
137 conf = timing & 0xFF;
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 * Program the UDMA timing for this drive according to the
154 static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
162 /* Program UDMA timing bits */
164 conf = timing >> 8;
166 conf = timing & 0xFF;
280 * timing register is private and we need only consider the clock. If
340 * Usually drivers set the DMA timing at the point the set_dmamode call
406 * perform out own device selection timing loads before the
444 * perform out own device selection timing loads before the