drivers/ata/pata_ep93xx.c

263 static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
267 	void __iomem *base = drv_data->ide_base;
268 	const struct ata_timing *t = &drv_data->t;
279 	ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
284 static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data,
287 	return ep93xx_pata_read(drv_data, addr, true);
291 static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data,
294 	return ep93xx_pata_read(drv_data, addr, false);
297 static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
301 	void __iomem *base = drv_data->ide_base;
302 	const struct ata_timing *t = &drv_data->t;
314 	ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
318 static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data,
321 	ep93xx_pata_write(drv_data, value, addr, true);
325 static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data,
328 	ep93xx_pata_write(drv_data, value, addr, false);
334 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
345 	ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0);
349 		ata_timing_merge(&t, &drv_data->t, &drv_data->t,
352 	drv_data->iordy = ata_pio_need_iordy(adev);
354 	ep93xx_pata_enable_pio(drv_data->ide_base,
361 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
363 	return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS);
368 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
370 	return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS);
377 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
381 		ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
387 		ep93xx_pata_write_reg(drv_data, tf->hob_feature,
389 		ep93xx_pata_write_reg(drv_data, tf->hob_nsect,
391 		ep93xx_pata_write_reg(drv_data, tf->hob_lbal,
393 		ep93xx_pata_write_reg(drv_data, tf->hob_lbam,
395 		ep93xx_pata_write_reg(drv_data, tf->hob_lbah,
400 		ep93xx_pata_write_reg(drv_data, tf->feature,
402 		ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT);
403 		ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL);
404 		ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM);
405 		ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH);
409 		ep93xx_pata_write_reg(drv_data, tf->device,
418 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
421 	tf->error = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
422 	tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
423 	tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
424 	tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM);
425 	tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH);
426 	tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE);
429 		ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB,
431 		tf->hob_feature = ep93xx_pata_read_reg(drv_data,
433 		tf->hob_nsect = ep93xx_pata_read_reg(drv_data,
435 		tf->hob_lbal = ep93xx_pata_read_reg(drv_data,
437 		tf->hob_lbam = ep93xx_pata_read_reg(drv_data,
439 		tf->hob_lbah = ep93xx_pata_read_reg(drv_data,
441 		ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
450 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
452 	ep93xx_pata_write_reg(drv_data, tf->command,
460 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
466 	ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE);
473 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
475 	ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL);
484 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
493 					drv_data, IDECTRL_ADDR_DATA));
495 			ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++),
507 					drv_data, IDECTRL_ADDR_DATA));
511 			ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad),
524 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
529 	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
530 	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
532 	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT);
533 	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL);
535 	ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
536 	ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
538 	nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
539 	lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
553 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
586 			nsect = ep93xx_pata_read_reg(drv_data,
588 			lbal = ep93xx_pata_read_reg(drv_data,
616 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
618 	ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
620 	ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL);
622 	ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
628 static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data)
630 	if (drv_data->dma_rx_channel) {
631 		dma_release_channel(drv_data->dma_rx_channel);
632 		drv_data->dma_rx_channel = NULL;
634 	if (drv_data->dma_tx_channel) {
635 		dma_release_channel(drv_data->dma_tx_channel);
636 		drv_data->dma_tx_channel = NULL;
649 static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
651 	const struct platform_device *pdev = drv_data->pdev;
663 	drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
664 	drv_data->dma_rx_data.direction = DMA_DEV_TO_MEM;
665 	drv_data->dma_rx_data.name = "ep93xx-pata-rx";
666 	drv_data->dma_rx_channel = dma_request_channel(mask,
667 		ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
668 	if (!drv_data->dma_rx_channel)
671 	drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
672 	drv_data->dma_tx_data.direction = DMA_MEM_TO_DEV;
673 	drv_data->dma_tx_data.name = "ep93xx-pata-tx";
674 	drv_data->dma_tx_channel = dma_request_channel(mask,
675 		ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
676 	if (!drv_data->dma_tx_channel) {
677 		dma_release_channel(drv_data->dma_rx_channel);
684 	conf.src_addr = drv_data->udma_in_phys;
686 	if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) {
688 		ep93xx_pata_release_dma(drv_data);
695 	conf.dst_addr = drv_data->udma_out_phys;
697 	if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) {
699 		ep93xx_pata_release_dma(drv_data);
706 	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
707 	void __iomem *base = drv_data->ide_base;
711 		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
746 	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
747 	void __iomem *base = drv_data->ide_base;
750 	dmaengine_terminate_all(drv_data->dma_rx_channel);
751 	dmaengine_terminate_all(drv_data->dma_tx_channel);
761 	ep93xx_pata_enable_pio(drv_data->ide_base,
774 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
775 	u32 val = readl(drv_data->ide_base + IDEUDMASTS);
795 	if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ)
846 	struct ep93xx_pata_data *drv_data;
853 	drv_data = ap->host->private_data;
857 		ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA);
866 	struct ep93xx_pata_data *drv_data = ap->host->private_data;
872 	drv_data->t = *ata_timing_find_mode(XFER_PIO_0);
922 	struct ep93xx_pata_data *drv_data;
947 	drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
948 	if (!drv_data) {
953 	drv_data->pdev = pdev;
954 	drv_data->ide_base = ide_base;
955 	drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
956 	drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
957 	ep93xx_pata_dma_init(drv_data);
968 	host->private_data = drv_data;
985 	if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
1007 	ep93xx_pata_release_dma(drv_data);
1016 	struct ep93xx_pata_data *drv_data = host->private_data;
1019 	ep93xx_pata_release_dma(drv_data);
1020 	ep93xx_pata_clear_regs(drv_data->ide_base);