drivers/ata/ahci_qoriq.c

61 	struct ccsr_ahci *reg_base;
167 	void __iomem *reg_base = hpriv->mmio;
175 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
176 		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
177 		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
178 		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
179 		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
180 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
183 					reg_base + LS1021A_AXICC_ADDR);
193 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
194 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
195 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
196 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
198 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
202 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
203 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
204 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
205 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
207 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
217 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
218 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
219 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
220 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
222 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
234 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
235 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
236 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
237 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
239 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
243 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
244 		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
245 		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
246 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
248 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);