accel/ivpu/vpu_boot_api.h

55 	u32 header_version;
56 	u32 image_format;
58 	u32 image_size;
61 	u32 compression_type;
63 	u32 firmware_version_size;
65 	u32 api_version[VPU_FW_API_VER_NUM];
67 	u32 runtime_size;
68 	u32 shave_nn_fw_size;
74 	u32 preemption_buffer_1_size;
80 	u32 preemption_buffer_2_size;
82 	u32 preemption_reserved[6];
171 	u32 src;
172 	u32 dst;
173 	u32 size;
174 	u32 core_id;
175 	u32 is_clear_op;
198 	u32 magic;
199 	u32 vpu_id;
200 	u32 vpu_count;
201 	u32 pad0[5];
203 	u32 frequency;
204 	u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
205 	u32 perf_clk_frequency;
206 	u32 pad1[42];
209 	u32 ipc_header_area_size;
211 	u32 shared_region_size;
213 	u32 ipc_payload_area_size;
215 	u32 global_aliased_pio_size;
216 	u32 autoconfig;
219 	u32 global_memory_allocator_size;
226 	u32 pad2[43];
231 	u32 host_to_vpu_irq;
233 	u32 job_done_irq;
235 	u32 mmu_update_request_irq;
237 	u32 mmu_update_done_irq;
239 	u32 set_power_level_irq;
241 	u32 set_power_level_done_irq;
243 	u32 set_vpu_idle_update_irq;
245 	u32 metric_query_event_irq;
247 	u32 metric_query_event_done_irq;
249 	u32 preemption_done_irq;
251 	u32 pad3[52];
253 	u32 host_version_id;
254 	u32 si_stepping;
259 	u32 min_freq_pll_ratio;
261 	u32 max_freq_pll_ratio;
269 	u32 default_trace_level;
270 	u32 boot_type;
273 	u32 vpu_telemetry_enable;
275 	u32 crit_tracing_buff_size;
277 	u32 verbose_tracing_buff_size;
283 	u32 trace_destination_mask;
296 	u32 temp_sensor_period_ms;
298 	u32 pn_freq_pll_ratio;
300 	u32 dvfs_mode;
323 	u32 d0i3_delayed_entry;
336 	u32 pad4[18];
338 	u32 warm_boot_sections_count;
339 	u32 warm_boot_start_address_reference;
340 	u32 warm_boot_section_info_address_offset;
341 	u32 pad5[13];
358 	u32 vpu_scheduling_mode;
360 	u32 vpu_focus_present_timer_ms;
362 	u32 vpu_uses_ecc_mca_signal;
364 	u32 power_profile;
366 	u32 dct_active_us;
368 	u32 dct_inactive_us;
370 	u32 pad6[734];
393 	u32 host_canary_start;
395 	u32 read_index;
396 	u32 pad_to_cache_line_size_0[14];
403 	u32 vpu_canary_start;
405 	u32 write_index;
407 	u32 wrap_count;
409 	u32 reserved_0;
415 	u32 size;
426 	u32 format;
432 	u32 alignment; /* 64, 128, 256 */
435 	u32 pad_to_cache_line_size_1[4];