accel/ivpu/ivpu_hw_40xx.c

170 	u32 val;
178 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);
179 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
180 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
181 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
183 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);
184 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
185 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val);
186 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val);
188 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);
189 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val);
190 	val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val);
191 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val);
193 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);
194 	val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val);
195 	REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val);
277 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);
280 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
281 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
282 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
284 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);
285 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);
286 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);
289 	REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
294 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);
297 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
298 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
299 		val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
301 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);
302 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);
303 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);
306 	REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
311 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
313 	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val))
321 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);
323 	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val))
331 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);
333 	if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val))
341 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
343 	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) ||
344 	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val))
352 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);
354 	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) ||
355 	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val))
363 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);
365 	if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) ||
366 	    !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val))
374 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);
377 		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
379 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);
381 	REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
410 	u32 val;
412 	val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);
414 		val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
416 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);
417 	REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
447 	u32 val;
449 	val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);
451 		val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
452 		val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
454 		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);
455 		val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);
457 	REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
479 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);
482 		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
484 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);
486 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
494 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
497 		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
499 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
501 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
518 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);
521 		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
523 		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);
525 	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
530 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);
532 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);
533 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);
534 	val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);
536 	REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
541 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);
543 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);
544 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);
545 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);
546 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);
547 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);
548 	val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);
550 	REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
555 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);
557 	if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val))
565 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);
567 	if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val))
608 	u32 val;
610 	val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);
612 		val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
614 		val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);
615 	REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
638 	u32 val;
651 	val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);
652 	val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);
653 	REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
664 	u32 val;
672 	val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);
674 		val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
676 		val = REG_CLR_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val);
677 	REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val);
747 	u32 val;
755 	val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);
756 	val = REG_SET_FLD(VPU_40XX_BUTTRESS_IP_RESET, TRIGGER, val);
757 	REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val);
815 	u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
818 		val = REG_CLR_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
820 		val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, PERF_CLK, val);
822 	REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
833 	u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
835 	val = REG_SET_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
836 	REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val);
901 	u32 val;
906 	val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);
907 	return REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, READY, val) &&
908 	       REG_TEST_FLD(VPU_40XX_BUTTRESS_VPU_STATUS, IDLE, val);
946 	u32 val;
954 	val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);
955 	val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);
956 	REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
1006 	u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);
1008 	REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val);