30 	u32 pb_addr, mask;
69 	mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2);
70 	mask |= 1 << ((mmMME_RESET & 0x7F) >> 2);
71 	mask |= 1 << ((mmMME_STALL & 0x7F) >> 2);
72 	mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
73 	mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
74 	mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2);
75 	mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2);
76 	mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2);
77 	mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2);
78 	mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2);
79 	mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2);
81 	WREG32(pb_addr + word_offset, ~mask);
85 	mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2);
86 	mask |= 1 << ((mmMME_AGU & 0x7F) >> 2);
87 	mask |= 1 << ((mmMME_SBA & 0x7F) >> 2);
88 	mask |= 1 << ((mmMME_SBB & 0x7F) >> 2);
89 	mask |= 1 << ((mmMME_SBC & 0x7F) >> 2);
90 	mask |= 1 << ((mmMME_WBC & 0x7F) >> 2);
91 	mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2);
92 	mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2);
93 	mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2);
94 	mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2);
95 	mask |= 1 << ((mmMME_TE & 0x7F) >> 2);
96 	mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2);
97 	mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2);
98 	mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2);
99 	mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2);
100 	mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2);
101 	mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2);
102 	mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2);
104 	WREG32(pb_addr + word_offset, ~mask);
108 	mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2);
109 	mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2);
110 	mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2);
111 	mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2);
112 	mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
113 	mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
114 	mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
115 	mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
116 	mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
117 	mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2);
118 	mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2);
119 	mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2);
120 	mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2);
121 	mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2);
122 	mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2);
123 	mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2);
124 	mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2);
125 	mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2);
126 	mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2);
128 	WREG32(pb_addr + word_offset, ~mask);
132 	mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2);
133 	mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2);
134 	mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2);
135 	mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2);
136 	mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2);
137 	mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2);
138 	mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
139 	mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
140 	mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
141 	mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
142 	mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2);
143 	mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2);
144 	mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2);
145 	mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2);
146 	mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2);
147 	mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2);
148 	mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2);
149 	mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
150 	mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
151 	mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2);
152 	mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2);
153 	mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2);
154 	mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2);
155 	mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
156 	mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
157 	mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
158 	mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
160 	WREG32(pb_addr + word_offset, ~mask);
164 	mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
165 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
166 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
167 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
168 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
169 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
170 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
171 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
172 	mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
173 	mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
174 	mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
175 	mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
176 	mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
177 	mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
178 	mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
180 	WREG32(pb_addr + word_offset, ~mask);
184 	mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2);
185 	mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2);
186 	mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2);
187 	mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2);
188 	mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2);
189 	mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2);
190 	mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2);
191 	mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2);
192 	mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2);
194 	WREG32(pb_addr + word_offset, ~mask);
198 	mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
199 	mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
200 	mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2);
201 	mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
202 	mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
203 	mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
204 	mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
205 	mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
206 	mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
207 	mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2);
208 	mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2);
210 	WREG32(pb_addr + word_offset, ~mask);
214 	mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2);
215 	mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2);
216 	mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2);
217 	mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
218 	mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
219 	mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
220 	mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
221 	mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2);
222 	mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2);
223 	mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
224 	mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
225 	mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
226 	mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
228 	WREG32(pb_addr + word_offset, ~mask);
233 	mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
234 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
235 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
236 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
237 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
238 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
239 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
240 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
241 	mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
242 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
243 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
244 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
245 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
246 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
247 	mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
248 	mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2);
249 	mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
251 	WREG32(pb_addr + word_offset, ~mask);
256 	mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
257 	mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
258 	mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2);
259 	mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
260 	mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
262 	WREG32(pb_addr + word_offset, ~mask);
266 	mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2);
267 	mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2);
269 	WREG32(pb_addr + word_offset, ~mask);
274 	u32 pb_addr, mask;
283 	mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2);
284 	mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2);
285 	mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2);
286 	mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2);
287 	mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
288 	mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
289 	mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2);
290 	mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2);
291 	mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
292 	mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2);
293 	mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2);
294 	mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2);
295 	mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2);
296 	mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2);
297 	mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2);
298 	mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2);
299 	mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2);
300 	mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2);
301 	mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2);
303 	WREG32(pb_addr + word_offset, ~mask);
307 	mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2);
308 	mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2);
309 	mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2);
310 	mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2);
311 	mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2);
312 	mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2);
313 	mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
314 	mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
315 	mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
316 	mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
317 	mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2);
318 	mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2);
319 	mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2);
320 	mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2);
321 	mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2);
322 	mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2);
323 	mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2);
324 	mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2);
325 	mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2);
326 	mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2);
327 	mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2);
328 	mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2);
329 	mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2);
330 	mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
331 	mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
332 	mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
333 	mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
335 	WREG32(pb_addr + word_offset, ~mask);
339 	mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2);
340 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
341 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
342 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
343 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
344 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
345 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
346 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
347 	mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
348 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
349 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
350 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
351 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
352 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
353 	mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
355 	WREG32(pb_addr + word_offset, ~mask);
361 	mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2);
362 	mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2);
363 	mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2);
364 	mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2);
365 	mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
366 	mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
367 	mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2);
368 	mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2);
369 	mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
370 	mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2);
371 	mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2);
372 	mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2);
373 	mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2);
374 	mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2);
375 	mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2);
376 	mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2);
377 	mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2);
378 	mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2);
379 	mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2);
381 	WREG32(pb_addr + word_offset, ~mask);
385 	mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2);
386 	mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2);
387 	mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2);
388 	mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2);
389 	mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2);
390 	mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2);
391 	mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
392 	mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
393 	mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
394 	mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
395 	mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2);
396 	mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2);
397 	mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2);
398 	mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2);
399 	mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2);
400 	mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2);
401 	mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2);
402 	mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2);
403 	mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2);
404 	mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2);
405 	mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2);
406 	mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2);
407 	mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2);
408 	mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
409 	mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
410 	mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
411 	mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
413 	WREG32(pb_addr + word_offset, ~mask);
417 	mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2);
418 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
419 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
420 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
421 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
422 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
423 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
424 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
425 	mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
426 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
427 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
428 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
429 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
430 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
431 	mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
433 	WREG32(pb_addr + word_offset, ~mask);
439 	mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2);
440 	mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2);
441 	mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2);
442 	mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2);
443 	mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
444 	mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
445 	mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2);
446 	mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2);
447 	mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
448 	mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2);
449 	mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2);
450 	mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2);
451 	mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2);
452 	mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2);
453 	mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2);
454 	mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2);
455 	mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2);
456 	mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2);
457 	mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2);
459 	WREG32(pb_addr + word_offset, ~mask);
463 	mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2);
464 	mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2);
465 	mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2);
466 	mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2);
467 	mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2);
468 	mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2);
469 	mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
470 	mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
471 	mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
472 	mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
473 	mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2);
474 	mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2);
475 	mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2);
476 	mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2);
477 	mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2);
478 	mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2);
479 	mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2);
480 	mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2);
481 	mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2);
482 	mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2);
483 	mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2);
484 	mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2);
485 	mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2);
486 	mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
487 	mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
488 	mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
489 	mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
491 	WREG32(pb_addr + word_offset, ~mask);
495 	mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2);
496 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
497 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
498 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
499 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
500 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
501 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
502 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
503 	mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
504 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
505 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
506 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
507 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
508 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
509 	mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
511 	WREG32(pb_addr + word_offset, ~mask);
517 	mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2);
518 	mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2);
519 	mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2);
520 	mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2);
521 	mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
522 	mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
523 	mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2);
524 	mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2);
525 	mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
526 	mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2);
527 	mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2);
528 	mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2);
529 	mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2);
530 	mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2);
531 	mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2);
532 	mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2);
533 	mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2);
534 	mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2);
535 	mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2);
537 	WREG32(pb_addr + word_offset, ~mask);
541 	mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2);
542 	mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2);
543 	mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2);
544 	mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2);
545 	mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2);
546 	mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2);
547 	mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
548 	mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
549 	mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
550 	mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
551 	mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2);
552 	mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2);
553 	mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2);
554 	mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2);
555 	mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2);
556 	mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2);
557 	mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2);
558 	mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2);
559 	mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2);
560 	mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2);
561 	mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2);
562 	mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2);
563 	mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2);
564 	mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
565 	mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
566 	mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
567 	mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
569 	WREG32(pb_addr + word_offset, ~mask);
573 	mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2);
574 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
575 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
576 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
577 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
578 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
579 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
580 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
581 	mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
582 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
583 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
584 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
585 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
586 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
587 	mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
589 	WREG32(pb_addr + word_offset, ~mask);
595 	mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2);
596 	mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2);
597 	mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2);
598 	mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2);
599 	mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
600 	mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
601 	mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2);
602 	mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2);
603 	mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
604 	mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2);
605 	mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2);
606 	mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2);
607 	mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2);
608 	mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2);
609 	mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2);
610 	mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2);
611 	mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2);
612 	mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2);
613 	mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2);
615 	WREG32(pb_addr + word_offset, ~mask);
619 	mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2);
620 	mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2);
621 	mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2);
622 	mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2);
623 	mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2);
624 	mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2);
625 	mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
626 	mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
627 	mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
628 	mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
629 	mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2);
630 	mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2);
631 	mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2);
632 	mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2);
633 	mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2);
634 	mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2);
635 	mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2);
636 	mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2);
637 	mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2);
638 	mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2);
639 	mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2);
640 	mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2);
641 	mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2);
642 	mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
643 	mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
644 	mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
645 	mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
647 	WREG32(pb_addr + word_offset, ~mask);
651 	mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2);
652 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
653 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
654 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
655 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
656 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
657 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
658 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
659 	mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
660 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
661 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
662 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
663 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
664 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
665 	mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
667 	WREG32(pb_addr + word_offset, ~mask);
674 	u32 pb_addr, mask;
683 	mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2);
684 	mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2);
685 	mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2);
686 	mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2);
688 	WREG32(pb_addr + word_offset, ~mask);
693 	mask = 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
694 	mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
695 	mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
696 	mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
697 	mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2);
698 	mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2);
699 	mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
700 	mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2);
702 	WREG32(pb_addr + word_offset, ~mask);
706 	mask = 1 << ((mmTPC0_CFG_ARUSER & 0x7F) >> 2);
707 	mask |= 1 << ((mmTPC0_CFG_AWUSER & 0x7F) >> 2);
709 	WREG32(pb_addr + word_offset, ~mask);
714 	mask = 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
715 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
716 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
717 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
718 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
719 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
720 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
721 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
722 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
723 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
724 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
725 	mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
727 	WREG32(pb_addr + word_offset, ~mask);
731 	mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2);
732 	mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2);
733 	mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2);
734 	mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2);
735 	mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
736 	mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
737 	mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
738 	mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
739 	mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
740 	mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2);
741 	mask |= 1 << ((mmTPC0_QM_GLBL_STS1 & 0x7F) >> 2);
742 	mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO & 0x7F) >> 2);
743 	mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI & 0x7F) >> 2);
744 	mask |= 1 << ((mmTPC0_QM_PQ_SIZE & 0x7F) >> 2);
745 	mask |= 1 << ((mmTPC0_QM_PQ_PI & 0x7F) >> 2);
746 	mask |= 1 << ((mmTPC0_QM_PQ_CI & 0x7F) >> 2);
747 	mask |= 1 << ((mmTPC0_QM_PQ_CFG0 & 0x7F) >> 2);
748 	mask |= 1 << ((mmTPC0_QM_PQ_CFG1 & 0x7F) >> 2);
749 	mask |= 1 << ((mmTPC0_QM_PQ_ARUSER & 0x7F) >> 2);
751 	WREG32(pb_addr + word_offset, ~mask);
755 	mask = 1 << ((mmTPC0_QM_PQ_PUSH0 & 0x7F) >> 2);
756 	mask |= 1 << ((mmTPC0_QM_PQ_PUSH1 & 0x7F) >> 2);
757 	mask |= 1 << ((mmTPC0_QM_PQ_PUSH2 & 0x7F) >> 2);
758 	mask |= 1 << ((mmTPC0_QM_PQ_PUSH3 & 0x7F) >> 2);
759 	mask |= 1 << ((mmTPC0_QM_PQ_STS0 & 0x7F) >> 2);
760 	mask |= 1 << ((mmTPC0_QM_PQ_STS1 & 0x7F) >> 2);
761 	mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
762 	mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
763 	mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
764 	mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
765 	mask |= 1 << ((mmTPC0_QM_CQ_CFG0 & 0x7F) >> 2);
766 	mask |= 1 << ((mmTPC0_QM_CQ_CFG1 & 0x7F) >> 2);
767 	mask |= 1 << ((mmTPC0_QM_CQ_ARUSER & 0x7F) >> 2);
768 	mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO & 0x7F) >> 2);
769 	mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI & 0x7F) >> 2);
770 	mask |= 1 << ((mmTPC0_QM_CQ_TSIZE & 0x7F) >> 2);
771 	mask |= 1 << ((mmTPC0_QM_CQ_CTL & 0x7F) >> 2);
772 	mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
773 	mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
774 	mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS & 0x7F) >> 2);
775 	mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS & 0x7F) >> 2);
776 	mask |= 1 << ((mmTPC0_QM_CQ_STS0 & 0x7F) >> 2);
777 	mask |= 1 << ((mmTPC0_QM_CQ_STS1 & 0x7F) >> 2);
778 	mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
779 	mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
780 	mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
781 	mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
783 	WREG32(pb_addr + word_offset, ~mask);
787 	mask = 1 << ((mmTPC0_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
788 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
789 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
790 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
791 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
792 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
793 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
794 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
795 	mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
796 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
797 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
798 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
799 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
800 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
801 	mask |= 1 << ((mmTPC0_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
803 	WREG32(pb_addr + word_offset, ~mask);
807 	mask = 1 << ((mmTPC0_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
808 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
809 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_PROT & 0x7F) >> 2);
810 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
811 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
812 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
813 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
814 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
815 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
816 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS0 & 0x7F) >> 2);
817 	mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS1 & 0x7F) >> 2);
819 	WREG32(pb_addr + word_offset, ~mask);
823 	mask = 1 << ((mmTPC0_CMDQ_CQ_CFG0 & 0x7F) >> 2);
824 	mask |= 1 << ((mmTPC0_CMDQ_CQ_CFG1 & 0x7F) >> 2);
825 	mask |= 1 << ((mmTPC0_CMDQ_CQ_ARUSER & 0x7F) >> 2);
826 	mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
827 	mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
828 	mask |= 1 << ((mmTPC0_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
829 	mask |= 1 << ((mmTPC0_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
830 	mask |= 1 << ((mmTPC0_CMDQ_CQ_STS0 & 0x7F) >> 2);
831 	mask |= 1 << ((mmTPC0_CMDQ_CQ_STS1 & 0x7F) >> 2);
832 	mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
833 	mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
834 	mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
835 	mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
837 	WREG32(pb_addr + word_offset, ~mask);
841 	mask = 1 << ((mmTPC0_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
842 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
843 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
844 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
845 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
846 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
847 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
848 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
849 	mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
850 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
851 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
852 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
853 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
854 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
855 	mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
856 	mask |= 1 << ((mmTPC0_CMDQ_CP_STS & 0x7F) >> 2);
857 	mask |= 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
859 	WREG32(pb_addr + word_offset, ~mask);
864 	mask = 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
865 	mask |= 1 << ((mmTPC0_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
866 	mask |= 1 << ((mmTPC0_CMDQ_CP_DBG_0 & 0x7F) >> 2);
867 	mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
868 	mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
870 	WREG32(pb_addr + word_offset, ~mask);
879 	mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2);
880 	mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2);
881 	mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2);
882 	mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2);
884 	WREG32(pb_addr + word_offset, ~mask);
889 	mask = 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
890 	mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
891 	mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
892 	mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
893 	mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2);
894 	mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2);
895 	mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
896 	mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2);
898 	WREG32(pb_addr + word_offset, ~mask);
902 	mask = 1 << ((mmTPC1_CFG_ARUSER & 0x7F) >> 2);
903 	mask |= 1 << ((mmTPC1_CFG_AWUSER & 0x7F) >> 2);
905 	WREG32(pb_addr + word_offset, ~mask);
910 	mask = 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
911 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
912 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
913 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
914 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
915 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
916 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
917 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
918 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
919 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
920 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
921 	mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
923 	WREG32(pb_addr + word_offset, ~mask);
927 	mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2);
928 	mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2);
929 	mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2);
930 	mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2);
931 	mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
932 	mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
933 	mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
934 	mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
935 	mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
936 	mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2);
937 	mask |= 1 << ((mmTPC1_QM_GLBL_STS1 & 0x7F) >> 2);
938 	mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO & 0x7F) >> 2);
939 	mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI & 0x7F) >> 2);
940 	mask |= 1 << ((mmTPC1_QM_PQ_SIZE & 0x7F) >> 2);
941 	mask |= 1 << ((mmTPC1_QM_PQ_PI & 0x7F) >> 2);
942 	mask |= 1 << ((mmTPC1_QM_PQ_CI & 0x7F) >> 2);
943 	mask |= 1 << ((mmTPC1_QM_PQ_CFG0 & 0x7F) >> 2);
944 	mask |= 1 << ((mmTPC1_QM_PQ_CFG1 & 0x7F) >> 2);
945 	mask |= 1 << ((mmTPC1_QM_PQ_ARUSER & 0x7F) >> 2);
947 	WREG32(pb_addr + word_offset, ~mask);
951 	mask = 1 << ((mmTPC1_QM_PQ_PUSH0 & 0x7F) >> 2);
952 	mask |= 1 << ((mmTPC1_QM_PQ_PUSH1 & 0x7F) >> 2);
953 	mask |= 1 << ((mmTPC1_QM_PQ_PUSH2 & 0x7F) >> 2);
954 	mask |= 1 << ((mmTPC1_QM_PQ_PUSH3 & 0x7F) >> 2);
955 	mask |= 1 << ((mmTPC1_QM_PQ_STS0 & 0x7F) >> 2);
956 	mask |= 1 << ((mmTPC1_QM_PQ_STS1 & 0x7F) >> 2);
957 	mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
958 	mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
959 	mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
960 	mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
961 	mask |= 1 << ((mmTPC1_QM_CQ_CFG0 & 0x7F) >> 2);
962 	mask |= 1 << ((mmTPC1_QM_CQ_CFG1 & 0x7F) >> 2);
963 	mask |= 1 << ((mmTPC1_QM_CQ_ARUSER & 0x7F) >> 2);
964 	mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO & 0x7F) >> 2);
965 	mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI & 0x7F) >> 2);
966 	mask |= 1 << ((mmTPC1_QM_CQ_TSIZE & 0x7F) >> 2);
967 	mask |= 1 << ((mmTPC1_QM_CQ_CTL & 0x7F) >> 2);
968 	mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
969 	mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
970 	mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS & 0x7F) >> 2);
971 	mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS & 0x7F) >> 2);
972 	mask |= 1 << ((mmTPC1_QM_CQ_STS0 & 0x7F) >> 2);
973 	mask |= 1 << ((mmTPC1_QM_CQ_STS1 & 0x7F) >> 2);
974 	mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
975 	mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
976 	mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
977 	mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
979 	WREG32(pb_addr + word_offset, ~mask);
983 	mask = 1 << ((mmTPC1_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
984 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
985 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
986 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
987 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
988 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
989 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
990 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
991 	mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
992 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
993 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
994 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
995 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
996 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
997 	mask |= 1 << ((mmTPC1_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
999 	WREG32(pb_addr + word_offset, ~mask);
1003 	mask = 1 << ((mmTPC1_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1004 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1005 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_PROT & 0x7F) >> 2);
1006 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1007 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1008 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1009 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1010 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1011 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1012 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1013 	mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1015 	WREG32(pb_addr + word_offset, ~mask);
1019 	mask = 1 << ((mmTPC1_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1020 	mask |= 1 << ((mmTPC1_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1021 	mask |= 1 << ((mmTPC1_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1022 	mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1023 	mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1024 	mask |= 1 << ((mmTPC1_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1025 	mask |= 1 << ((mmTPC1_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1026 	mask |= 1 << ((mmTPC1_CMDQ_CQ_STS0 & 0x7F) >> 2);
1027 	mask |= 1 << ((mmTPC1_CMDQ_CQ_STS1 & 0x7F) >> 2);
1028 	mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1029 	mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1030 	mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1031 	mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1033 	WREG32(pb_addr + word_offset, ~mask);
1037 	mask = 1 << ((mmTPC1_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1038 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1039 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1040 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1041 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1042 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1043 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1044 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1045 	mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1046 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1047 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1048 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1049 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1050 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1051 	mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1052 	mask |= 1 << ((mmTPC1_CMDQ_CP_STS & 0x7F) >> 2);
1053 	mask |= 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1055 	WREG32(pb_addr + word_offset, ~mask);
1060 	mask = 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1061 	mask |= 1 << ((mmTPC1_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1062 	mask |= 1 << ((mmTPC1_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1063 	mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1064 	mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1066 	WREG32(pb_addr + word_offset, ~mask);
1075 	mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2);
1076 	mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2);
1077 	mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2);
1078 	mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2);
1080 	WREG32(pb_addr + word_offset, ~mask);
1085 	mask = 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1086 	mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1087 	mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1088 	mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1089 	mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2);
1090 	mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2);
1091 	mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1092 	mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1094 	WREG32(pb_addr + word_offset, ~mask);
1098 	mask = 1 << ((mmTPC2_CFG_ARUSER & 0x7F) >> 2);
1099 	mask |= 1 << ((mmTPC2_CFG_AWUSER & 0x7F) >> 2);
1101 	WREG32(pb_addr + word_offset, ~mask);
1106 	mask = 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1107 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1108 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1109 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1110 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1111 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1112 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1113 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1114 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1115 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1116 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1117 	mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1119 	WREG32(pb_addr + word_offset, ~mask);
1123 	mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2);
1124 	mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2);
1125 	mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2);
1126 	mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1127 	mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1128 	mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1129 	mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1130 	mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1131 	mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1132 	mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2);
1133 	mask |= 1 << ((mmTPC2_QM_GLBL_STS1 & 0x7F) >> 2);
1134 	mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO & 0x7F) >> 2);
1135 	mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI & 0x7F) >> 2);
1136 	mask |= 1 << ((mmTPC2_QM_PQ_SIZE & 0x7F) >> 2);
1137 	mask |= 1 << ((mmTPC2_QM_PQ_PI & 0x7F) >> 2);
1138 	mask |= 1 << ((mmTPC2_QM_PQ_CI & 0x7F) >> 2);
1139 	mask |= 1 << ((mmTPC2_QM_PQ_CFG0 & 0x7F) >> 2);
1140 	mask |= 1 << ((mmTPC2_QM_PQ_CFG1 & 0x7F) >> 2);
1141 	mask |= 1 << ((mmTPC2_QM_PQ_ARUSER & 0x7F) >> 2);
1143 	WREG32(pb_addr + word_offset, ~mask);
1147 	mask = 1 << ((mmTPC2_QM_PQ_PUSH0 & 0x7F) >> 2);
1148 	mask |= 1 << ((mmTPC2_QM_PQ_PUSH1 & 0x7F) >> 2);
1149 	mask |= 1 << ((mmTPC2_QM_PQ_PUSH2 & 0x7F) >> 2);
1150 	mask |= 1 << ((mmTPC2_QM_PQ_PUSH3 & 0x7F) >> 2);
1151 	mask |= 1 << ((mmTPC2_QM_PQ_STS0 & 0x7F) >> 2);
1152 	mask |= 1 << ((mmTPC2_QM_PQ_STS1 & 0x7F) >> 2);
1153 	mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1154 	mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1155 	mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1156 	mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1157 	mask |= 1 << ((mmTPC2_QM_CQ_CFG0 & 0x7F) >> 2);
1158 	mask |= 1 << ((mmTPC2_QM_CQ_CFG1 & 0x7F) >> 2);
1159 	mask |= 1 << ((mmTPC2_QM_CQ_ARUSER & 0x7F) >> 2);
1160 	mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO & 0x7F) >> 2);
1161 	mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI & 0x7F) >> 2);
1162 	mask |= 1 << ((mmTPC2_QM_CQ_TSIZE & 0x7F) >> 2);
1163 	mask |= 1 << ((mmTPC2_QM_CQ_CTL & 0x7F) >> 2);
1164 	mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1165 	mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1166 	mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1167 	mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS & 0x7F) >> 2);
1168 	mask |= 1 << ((mmTPC2_QM_CQ_STS0 & 0x7F) >> 2);
1169 	mask |= 1 << ((mmTPC2_QM_CQ_STS1 & 0x7F) >> 2);
1170 	mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1171 	mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1172 	mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1173 	mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1175 	WREG32(pb_addr + word_offset, ~mask);
1179 	mask = 1 << ((mmTPC2_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1180 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1181 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1182 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1183 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1184 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1185 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1186 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1187 	mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1188 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1189 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1190 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1191 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1192 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1193 	mask |= 1 << ((mmTPC2_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1195 	WREG32(pb_addr + word_offset, ~mask);
1199 	mask = 1 << ((mmTPC2_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1200 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1201 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_PROT & 0x7F) >> 2);
1202 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1203 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1204 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1205 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1206 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1207 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1208 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1209 	mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1211 	WREG32(pb_addr + word_offset, ~mask);
1215 	mask = 1 << ((mmTPC2_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1216 	mask |= 1 << ((mmTPC2_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1217 	mask |= 1 << ((mmTPC2_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1218 	mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1219 	mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1220 	mask |= 1 << ((mmTPC2_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1221 	mask |= 1 << ((mmTPC2_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1222 	mask |= 1 << ((mmTPC2_CMDQ_CQ_STS0 & 0x7F) >> 2);
1223 	mask |= 1 << ((mmTPC2_CMDQ_CQ_STS1 & 0x7F) >> 2);
1224 	mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1225 	mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1226 	mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1227 	mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1229 	WREG32(pb_addr + word_offset, ~mask);
1233 	mask = 1 << ((mmTPC2_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1234 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1235 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1236 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1237 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1238 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1239 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1240 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1241 	mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1242 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1243 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1244 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1245 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1246 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1247 	mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1248 	mask |= 1 << ((mmTPC2_CMDQ_CP_STS & 0x7F) >> 2);
1249 	mask |= 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1251 	WREG32(pb_addr + word_offset, ~mask);
1256 	mask = 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1257 	mask |= 1 << ((mmTPC2_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1258 	mask |= 1 << ((mmTPC2_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1259 	mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1260 	mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1262 	WREG32(pb_addr + word_offset, ~mask);
1271 	mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2);
1272 	mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2);
1273 	mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2);
1274 	mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2);
1276 	WREG32(pb_addr + word_offset, ~mask);
1281 	mask = 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1282 	mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1283 	mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1284 	mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1285 	mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2);
1286 	mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2);
1287 	mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1288 	mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1290 	WREG32(pb_addr + word_offset, ~mask);
1294 	mask = 1 << ((mmTPC3_CFG_ARUSER & 0x7F) >> 2);
1295 	mask |= 1 << ((mmTPC3_CFG_AWUSER & 0x7F) >> 2);
1297 	WREG32(pb_addr + word_offset, ~mask);
1302 	mask = 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1303 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1304 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1305 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1306 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1307 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1308 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1309 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1310 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1311 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1312 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1313 	mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1315 	WREG32(pb_addr + word_offset, ~mask);
1319 	mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2);
1320 	mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2);
1321 	mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2);
1322 	mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1323 	mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1324 	mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1325 	mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1326 	mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1327 	mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1328 	mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2);
1329 	mask |= 1 << ((mmTPC3_QM_GLBL_STS1 & 0x7F) >> 2);
1330 	mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO & 0x7F) >> 2);
1331 	mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI & 0x7F) >> 2);
1332 	mask |= 1 << ((mmTPC3_QM_PQ_SIZE & 0x7F) >> 2);
1333 	mask |= 1 << ((mmTPC3_QM_PQ_PI & 0x7F) >> 2);
1334 	mask |= 1 << ((mmTPC3_QM_PQ_CI & 0x7F) >> 2);
1335 	mask |= 1 << ((mmTPC3_QM_PQ_CFG0 & 0x7F) >> 2);
1336 	mask |= 1 << ((mmTPC3_QM_PQ_CFG1 & 0x7F) >> 2);
1337 	mask |= 1 << ((mmTPC3_QM_PQ_ARUSER & 0x7F) >> 2);
1339 	WREG32(pb_addr + word_offset, ~mask);
1343 	mask = 1 << ((mmTPC3_QM_PQ_PUSH0 & 0x7F) >> 2);
1344 	mask |= 1 << ((mmTPC3_QM_PQ_PUSH1 & 0x7F) >> 2);
1345 	mask |= 1 << ((mmTPC3_QM_PQ_PUSH2 & 0x7F) >> 2);
1346 	mask |= 1 << ((mmTPC3_QM_PQ_PUSH3 & 0x7F) >> 2);
1347 	mask |= 1 << ((mmTPC3_QM_PQ_STS0 & 0x7F) >> 2);
1348 	mask |= 1 << ((mmTPC3_QM_PQ_STS1 & 0x7F) >> 2);
1349 	mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1350 	mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1351 	mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1352 	mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1353 	mask |= 1 << ((mmTPC3_QM_CQ_CFG0 & 0x7F) >> 2);
1354 	mask |= 1 << ((mmTPC3_QM_CQ_CFG1 & 0x7F) >> 2);
1355 	mask |= 1 << ((mmTPC3_QM_CQ_ARUSER & 0x7F) >> 2);
1356 	mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO & 0x7F) >> 2);
1357 	mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI & 0x7F) >> 2);
1358 	mask |= 1 << ((mmTPC3_QM_CQ_TSIZE & 0x7F) >> 2);
1359 	mask |= 1 << ((mmTPC3_QM_CQ_CTL & 0x7F) >> 2);
1360 	mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1361 	mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1362 	mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1363 	mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS & 0x7F) >> 2);
1364 	mask |= 1 << ((mmTPC3_QM_CQ_STS0 & 0x7F) >> 2);
1365 	mask |= 1 << ((mmTPC3_QM_CQ_STS1 & 0x7F) >> 2);
1366 	mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1367 	mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1368 	mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1369 	mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1371 	WREG32(pb_addr + word_offset, ~mask);
1375 	mask = 1 << ((mmTPC3_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1376 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1377 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1378 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1379 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1380 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1381 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1382 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1383 	mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1384 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1385 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1386 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1387 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1388 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1389 	mask |= 1 << ((mmTPC3_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1391 	WREG32(pb_addr + word_offset, ~mask);
1395 	mask = 1 << ((mmTPC3_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1396 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1397 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_PROT & 0x7F) >> 2);
1398 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1399 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1400 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1401 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1402 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1403 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1404 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1405 	mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1407 	WREG32(pb_addr + word_offset, ~mask);
1411 	mask = 1 << ((mmTPC3_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1412 	mask |= 1 << ((mmTPC3_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1413 	mask |= 1 << ((mmTPC3_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1414 	mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1415 	mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1416 	mask |= 1 << ((mmTPC3_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1417 	mask |= 1 << ((mmTPC3_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1418 	mask |= 1 << ((mmTPC3_CMDQ_CQ_STS0 & 0x7F) >> 2);
1419 	mask |= 1 << ((mmTPC3_CMDQ_CQ_STS1 & 0x7F) >> 2);
1420 	mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1421 	mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1422 	mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1423 	mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1425 	WREG32(pb_addr + word_offset, ~mask);
1429 	mask = 1 << ((mmTPC3_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1430 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1431 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1432 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1433 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1434 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1435 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1436 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1437 	mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1438 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1439 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1440 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1441 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1442 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1443 	mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1444 	mask |= 1 << ((mmTPC3_CMDQ_CP_STS & 0x7F) >> 2);
1445 	mask |= 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1447 	WREG32(pb_addr + word_offset, ~mask);
1452 	mask = 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1453 	mask |= 1 << ((mmTPC3_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1454 	mask |= 1 << ((mmTPC3_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1455 	mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1456 	mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1458 	WREG32(pb_addr + word_offset, ~mask);
1467 	mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2);
1468 	mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2);
1469 	mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2);
1470 	mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2);
1472 	WREG32(pb_addr + word_offset, ~mask);
1477 	mask = 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1478 	mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1479 	mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1480 	mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1481 	mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2);
1482 	mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2);
1483 	mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1484 	mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1486 	WREG32(pb_addr + word_offset, ~mask);
1490 	mask = 1 << ((mmTPC4_CFG_ARUSER & 0x7F) >> 2);
1491 	mask |= 1 << ((mmTPC4_CFG_AWUSER & 0x7F) >> 2);
1493 	WREG32(pb_addr + word_offset, ~mask);
1498 	mask = 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1499 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1500 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1501 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1502 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1503 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1504 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1505 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1506 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1507 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1508 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1509 	mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1511 	WREG32(pb_addr + word_offset, ~mask);
1515 	mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2);
1516 	mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2);
1517 	mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2);
1518 	mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1519 	mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1520 	mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1521 	mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1522 	mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1523 	mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1524 	mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2);
1525 	mask |= 1 << ((mmTPC4_QM_GLBL_STS1 & 0x7F) >> 2);
1526 	mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO & 0x7F) >> 2);
1527 	mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI & 0x7F) >> 2);
1528 	mask |= 1 << ((mmTPC4_QM_PQ_SIZE & 0x7F) >> 2);
1529 	mask |= 1 << ((mmTPC4_QM_PQ_PI & 0x7F) >> 2);
1530 	mask |= 1 << ((mmTPC4_QM_PQ_CI & 0x7F) >> 2);
1531 	mask |= 1 << ((mmTPC4_QM_PQ_CFG0 & 0x7F) >> 2);
1532 	mask |= 1 << ((mmTPC4_QM_PQ_CFG1 & 0x7F) >> 2);
1533 	mask |= 1 << ((mmTPC4_QM_PQ_ARUSER & 0x7F) >> 2);
1535 	WREG32(pb_addr + word_offset, ~mask);
1539 	mask = 1 << ((mmTPC4_QM_PQ_PUSH0 & 0x7F) >> 2);
1540 	mask |= 1 << ((mmTPC4_QM_PQ_PUSH1 & 0x7F) >> 2);
1541 	mask |= 1 << ((mmTPC4_QM_PQ_PUSH2 & 0x7F) >> 2);
1542 	mask |= 1 << ((mmTPC4_QM_PQ_PUSH3 & 0x7F) >> 2);
1543 	mask |= 1 << ((mmTPC4_QM_PQ_STS0 & 0x7F) >> 2);
1544 	mask |= 1 << ((mmTPC4_QM_PQ_STS1 & 0x7F) >> 2);
1545 	mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1546 	mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1547 	mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1548 	mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1549 	mask |= 1 << ((mmTPC4_QM_CQ_CFG0 & 0x7F) >> 2);
1550 	mask |= 1 << ((mmTPC4_QM_CQ_CFG1 & 0x7F) >> 2);
1551 	mask |= 1 << ((mmTPC4_QM_CQ_ARUSER & 0x7F) >> 2);
1552 	mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO & 0x7F) >> 2);
1553 	mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI & 0x7F) >> 2);
1554 	mask |= 1 << ((mmTPC4_QM_CQ_TSIZE & 0x7F) >> 2);
1555 	mask |= 1 << ((mmTPC4_QM_CQ_CTL & 0x7F) >> 2);
1556 	mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1557 	mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1558 	mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1559 	mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS & 0x7F) >> 2);
1560 	mask |= 1 << ((mmTPC4_QM_CQ_STS0 & 0x7F) >> 2);
1561 	mask |= 1 << ((mmTPC4_QM_CQ_STS1 & 0x7F) >> 2);
1562 	mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1563 	mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1564 	mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1565 	mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1567 	WREG32(pb_addr + word_offset, ~mask);
1571 	mask = 1 << ((mmTPC4_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1572 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1573 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1574 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1575 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1576 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1577 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1578 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1579 	mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1580 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1581 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1582 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1583 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1584 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1585 	mask |= 1 << ((mmTPC4_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1587 	WREG32(pb_addr + word_offset, ~mask);
1591 	mask = 1 << ((mmTPC4_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1592 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1593 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_PROT & 0x7F) >> 2);
1594 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1595 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1596 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1597 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1598 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1599 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1600 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1601 	mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1603 	WREG32(pb_addr + word_offset, ~mask);
1607 	mask = 1 << ((mmTPC4_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1608 	mask |= 1 << ((mmTPC4_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1609 	mask |= 1 << ((mmTPC4_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1610 	mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1611 	mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1612 	mask |= 1 << ((mmTPC4_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1613 	mask |= 1 << ((mmTPC4_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1614 	mask |= 1 << ((mmTPC4_CMDQ_CQ_STS0 & 0x7F) >> 2);
1615 	mask |= 1 << ((mmTPC4_CMDQ_CQ_STS1 & 0x7F) >> 2);
1616 	mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1617 	mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1618 	mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1619 	mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1621 	WREG32(pb_addr + word_offset, ~mask);
1625 	mask = 1 << ((mmTPC4_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1626 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1627 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1628 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1629 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1630 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1631 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1632 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1633 	mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1634 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1635 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1636 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1637 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1638 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1639 	mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1640 	mask |= 1 << ((mmTPC4_CMDQ_CP_STS & 0x7F) >> 2);
1641 	mask |= 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1643 	WREG32(pb_addr + word_offset, ~mask);
1648 	mask = 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1649 	mask |= 1 << ((mmTPC4_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1650 	mask |= 1 << ((mmTPC4_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1651 	mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1652 	mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1654 	WREG32(pb_addr + word_offset, ~mask);
1663 	mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2);
1664 	mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2);
1665 	mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2);
1666 	mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2);
1668 	WREG32(pb_addr + word_offset, ~mask);
1673 	mask = 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1674 	mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1675 	mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1676 	mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1677 	mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2);
1678 	mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2);
1679 	mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1680 	mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1682 	WREG32(pb_addr + word_offset, ~mask);
1686 	mask = 1 << ((mmTPC5_CFG_ARUSER & 0x7F) >> 2);
1687 	mask |= 1 << ((mmTPC5_CFG_AWUSER & 0x7F) >> 2);
1689 	WREG32(pb_addr + word_offset, ~mask);
1694 	mask = 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1695 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1696 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1697 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1698 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1699 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1700 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1701 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1702 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1703 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1704 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1705 	mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1707 	WREG32(pb_addr + word_offset, ~mask);
1711 	mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2);
1712 	mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2);
1713 	mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2);
1714 	mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1715 	mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1716 	mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1717 	mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1718 	mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1719 	mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1720 	mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2);
1721 	mask |= 1 << ((mmTPC5_QM_GLBL_STS1 & 0x7F) >> 2);
1722 	mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO & 0x7F) >> 2);
1723 	mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI & 0x7F) >> 2);
1724 	mask |= 1 << ((mmTPC5_QM_PQ_SIZE & 0x7F) >> 2);
1725 	mask |= 1 << ((mmTPC5_QM_PQ_PI & 0x7F) >> 2);
1726 	mask |= 1 << ((mmTPC5_QM_PQ_CI & 0x7F) >> 2);
1727 	mask |= 1 << ((mmTPC5_QM_PQ_CFG0 & 0x7F) >> 2);
1728 	mask |= 1 << ((mmTPC5_QM_PQ_CFG1 & 0x7F) >> 2);
1729 	mask |= 1 << ((mmTPC5_QM_PQ_ARUSER & 0x7F) >> 2);
1731 	WREG32(pb_addr + word_offset, ~mask);
1735 	mask = 1 << ((mmTPC5_QM_PQ_PUSH0 & 0x7F) >> 2);
1736 	mask |= 1 << ((mmTPC5_QM_PQ_PUSH1 & 0x7F) >> 2);
1737 	mask |= 1 << ((mmTPC5_QM_PQ_PUSH2 & 0x7F) >> 2);
1738 	mask |= 1 << ((mmTPC5_QM_PQ_PUSH3 & 0x7F) >> 2);
1739 	mask |= 1 << ((mmTPC5_QM_PQ_STS0 & 0x7F) >> 2);
1740 	mask |= 1 << ((mmTPC5_QM_PQ_STS1 & 0x7F) >> 2);
1741 	mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1742 	mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1743 	mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1744 	mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1745 	mask |= 1 << ((mmTPC5_QM_CQ_CFG0 & 0x7F) >> 2);
1746 	mask |= 1 << ((mmTPC5_QM_CQ_CFG1 & 0x7F) >> 2);
1747 	mask |= 1 << ((mmTPC5_QM_CQ_ARUSER & 0x7F) >> 2);
1748 	mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO & 0x7F) >> 2);
1749 	mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI & 0x7F) >> 2);
1750 	mask |= 1 << ((mmTPC5_QM_CQ_TSIZE & 0x7F) >> 2);
1751 	mask |= 1 << ((mmTPC5_QM_CQ_CTL & 0x7F) >> 2);
1752 	mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1753 	mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1754 	mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1755 	mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS & 0x7F) >> 2);
1756 	mask |= 1 << ((mmTPC5_QM_CQ_STS0 & 0x7F) >> 2);
1757 	mask |= 1 << ((mmTPC5_QM_CQ_STS1 & 0x7F) >> 2);
1758 	mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1759 	mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1760 	mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1761 	mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1763 	WREG32(pb_addr + word_offset, ~mask);
1767 	mask = 1 << ((mmTPC5_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1768 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1769 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1770 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1771 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1772 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1773 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1774 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1775 	mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1776 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1777 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1778 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1779 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1780 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1781 	mask |= 1 << ((mmTPC5_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1783 	WREG32(pb_addr + word_offset, ~mask);
1787 	mask = 1 << ((mmTPC5_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1788 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1789 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_PROT & 0x7F) >> 2);
1790 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1791 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1792 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1793 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1794 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1795 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1796 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1797 	mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1799 	WREG32(pb_addr + word_offset, ~mask);
1803 	mask = 1 << ((mmTPC5_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1804 	mask |= 1 << ((mmTPC5_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1805 	mask |= 1 << ((mmTPC5_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1806 	mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1807 	mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1808 	mask |= 1 << ((mmTPC5_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1809 	mask |= 1 << ((mmTPC5_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1810 	mask |= 1 << ((mmTPC5_CMDQ_CQ_STS0 & 0x7F) >> 2);
1811 	mask |= 1 << ((mmTPC5_CMDQ_CQ_STS1 & 0x7F) >> 2);
1812 	mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1813 	mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1814 	mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1815 	mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1817 	WREG32(pb_addr + word_offset, ~mask);
1821 	mask = 1 << ((mmTPC5_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1822 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1823 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1824 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1825 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1826 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1827 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1828 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1829 	mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1830 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1831 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1832 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1833 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1834 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1835 	mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1836 	mask |= 1 << ((mmTPC5_CMDQ_CP_STS & 0x7F) >> 2);
1837 	mask |= 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1839 	WREG32(pb_addr + word_offset, ~mask);
1844 	mask = 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1845 	mask |= 1 << ((mmTPC5_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1846 	mask |= 1 << ((mmTPC5_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1847 	mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1848 	mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1850 	WREG32(pb_addr + word_offset, ~mask);
1859 	mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2);
1860 	mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2);
1861 	mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2);
1862 	mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2);
1864 	WREG32(pb_addr + word_offset, ~mask);
1869 	mask = 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1870 	mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1871 	mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1872 	mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1873 	mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2);
1874 	mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2);
1875 	mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1876 	mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1878 	WREG32(pb_addr + word_offset, ~mask);
1882 	mask = 1 << ((mmTPC6_CFG_ARUSER & 0x7F) >> 2);
1883 	mask |= 1 << ((mmTPC6_CFG_AWUSER & 0x7F) >> 2);
1885 	WREG32(pb_addr + word_offset, ~mask);
1890 	mask = 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1891 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1892 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1893 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1894 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1895 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1896 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1897 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1898 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1899 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1900 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1901 	mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1903 	WREG32(pb_addr + word_offset, ~mask);
1907 	mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2);
1908 	mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2);
1909 	mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2);
1910 	mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1911 	mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1912 	mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1913 	mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1914 	mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1915 	mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1916 	mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2);
1917 	mask |= 1 << ((mmTPC6_QM_GLBL_STS1 & 0x7F) >> 2);
1918 	mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO & 0x7F) >> 2);
1919 	mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI & 0x7F) >> 2);
1920 	mask |= 1 << ((mmTPC6_QM_PQ_SIZE & 0x7F) >> 2);
1921 	mask |= 1 << ((mmTPC6_QM_PQ_PI & 0x7F) >> 2);
1922 	mask |= 1 << ((mmTPC6_QM_PQ_CI & 0x7F) >> 2);
1923 	mask |= 1 << ((mmTPC6_QM_PQ_CFG0 & 0x7F) >> 2);
1924 	mask |= 1 << ((mmTPC6_QM_PQ_CFG1 & 0x7F) >> 2);
1925 	mask |= 1 << ((mmTPC6_QM_PQ_ARUSER & 0x7F) >> 2);
1927 	WREG32(pb_addr + word_offset, ~mask);
1931 	mask = 1 << ((mmTPC6_QM_PQ_PUSH0 & 0x7F) >> 2);
1932 	mask |= 1 << ((mmTPC6_QM_PQ_PUSH1 & 0x7F) >> 2);
1933 	mask |= 1 << ((mmTPC6_QM_PQ_PUSH2 & 0x7F) >> 2);
1934 	mask |= 1 << ((mmTPC6_QM_PQ_PUSH3 & 0x7F) >> 2);
1935 	mask |= 1 << ((mmTPC6_QM_PQ_STS0 & 0x7F) >> 2);
1936 	mask |= 1 << ((mmTPC6_QM_PQ_STS1 & 0x7F) >> 2);
1937 	mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1938 	mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1939 	mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1940 	mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1941 	mask |= 1 << ((mmTPC6_QM_CQ_CFG0 & 0x7F) >> 2);
1942 	mask |= 1 << ((mmTPC6_QM_CQ_CFG1 & 0x7F) >> 2);
1943 	mask |= 1 << ((mmTPC6_QM_CQ_ARUSER & 0x7F) >> 2);
1944 	mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO & 0x7F) >> 2);
1945 	mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI & 0x7F) >> 2);
1946 	mask |= 1 << ((mmTPC6_QM_CQ_TSIZE & 0x7F) >> 2);
1947 	mask |= 1 << ((mmTPC6_QM_CQ_CTL & 0x7F) >> 2);
1948 	mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1949 	mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1950 	mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1951 	mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS & 0x7F) >> 2);
1952 	mask |= 1 << ((mmTPC6_QM_CQ_STS0 & 0x7F) >> 2);
1953 	mask |= 1 << ((mmTPC6_QM_CQ_STS1 & 0x7F) >> 2);
1954 	mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1955 	mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1956 	mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1957 	mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1959 	WREG32(pb_addr + word_offset, ~mask);
1963 	mask = 1 << ((mmTPC6_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1964 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1965 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1966 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1967 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1968 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1969 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1970 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1971 	mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1972 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1973 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1974 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1975 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1976 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1977 	mask |= 1 << ((mmTPC6_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1979 	WREG32(pb_addr + word_offset, ~mask);
1983 	mask = 1 << ((mmTPC6_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1984 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1985 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_PROT & 0x7F) >> 2);
1986 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1987 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1988 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1989 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1990 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1991 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1992 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1993 	mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1995 	WREG32(pb_addr + word_offset, ~mask);
1999 	mask = 1 << ((mmTPC6_CMDQ_CQ_CFG0 & 0x7F) >> 2);
2000 	mask |= 1 << ((mmTPC6_CMDQ_CQ_CFG1 & 0x7F) >> 2);
2001 	mask |= 1 << ((mmTPC6_CMDQ_CQ_ARUSER & 0x7F) >> 2);
2002 	mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
2003 	mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
2004 	mask |= 1 << ((mmTPC6_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
2005 	mask |= 1 << ((mmTPC6_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
2006 	mask |= 1 << ((mmTPC6_CMDQ_CQ_STS0 & 0x7F) >> 2);
2007 	mask |= 1 << ((mmTPC6_CMDQ_CQ_STS1 & 0x7F) >> 2);
2008 	mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2009 	mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2010 	mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2011 	mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2013 	WREG32(pb_addr + word_offset, ~mask);
2017 	mask = 1 << ((mmTPC6_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
2018 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2019 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2020 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2021 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2022 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2023 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2024 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2025 	mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2026 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2027 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2028 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2029 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2030 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2031 	mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2032 	mask |= 1 << ((mmTPC6_CMDQ_CP_STS & 0x7F) >> 2);
2033 	mask |= 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
2035 	WREG32(pb_addr + word_offset, ~mask);
2040 	mask = 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
2041 	mask |= 1 << ((mmTPC6_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
2042 	mask |= 1 << ((mmTPC6_CMDQ_CP_DBG_0 & 0x7F) >> 2);
2043 	mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
2044 	mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
2046 	WREG32(pb_addr + word_offset, ~mask);
2055 	mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2);
2056 	mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2);
2057 	mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2);
2058 	mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2);
2060 	WREG32(pb_addr + word_offset, ~mask);
2065 	mask = 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
2066 	mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
2067 	mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
2068 	mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
2069 	mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2);
2070 	mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2);
2071 	mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
2072 	mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2);
2074 	WREG32(pb_addr + word_offset, ~mask);
2078 	mask = 1 << ((mmTPC7_CFG_ARUSER & 0x7F) >> 2);
2079 	mask |= 1 << ((mmTPC7_CFG_AWUSER & 0x7F) >> 2);
2081 	WREG32(pb_addr + word_offset, ~mask);
2086 	mask = 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
2087 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
2088 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
2089 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
2090 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
2091 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
2092 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
2093 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
2094 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
2095 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
2096 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
2097 	mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
2099 	WREG32(pb_addr + word_offset, ~mask);
2103 	mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2);
2104 	mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2);
2105 	mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2);
2106 	mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2);
2107 	mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
2108 	mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
2109 	mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
2110 	mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
2111 	mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
2112 	mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2);
2113 	mask |= 1 << ((mmTPC7_QM_GLBL_STS1 & 0x7F) >> 2);
2114 	mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO & 0x7F) >> 2);
2115 	mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI & 0x7F) >> 2);
2116 	mask |= 1 << ((mmTPC7_QM_PQ_SIZE & 0x7F) >> 2);
2117 	mask |= 1 << ((mmTPC7_QM_PQ_PI & 0x7F) >> 2);
2118 	mask |= 1 << ((mmTPC7_QM_PQ_CI & 0x7F) >> 2);
2119 	mask |= 1 << ((mmTPC7_QM_PQ_CFG0 & 0x7F) >> 2);
2120 	mask |= 1 << ((mmTPC7_QM_PQ_CFG1 & 0x7F) >> 2);
2121 	mask |= 1 << ((mmTPC7_QM_PQ_ARUSER & 0x7F) >> 2);
2123 	WREG32(pb_addr + word_offset, ~mask);
2127 	mask = 1 << ((mmTPC7_QM_PQ_PUSH0 & 0x7F) >> 2);
2128 	mask |= 1 << ((mmTPC7_QM_PQ_PUSH1 & 0x7F) >> 2);
2129 	mask |= 1 << ((mmTPC7_QM_PQ_PUSH2 & 0x7F) >> 2);
2130 	mask |= 1 << ((mmTPC7_QM_PQ_PUSH3 & 0x7F) >> 2);
2131 	mask |= 1 << ((mmTPC7_QM_PQ_STS0 & 0x7F) >> 2);
2132 	mask |= 1 << ((mmTPC7_QM_PQ_STS1 & 0x7F) >> 2);
2133 	mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2134 	mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2135 	mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2136 	mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2137 	mask |= 1 << ((mmTPC7_QM_CQ_CFG0 & 0x7F) >> 2);
2138 	mask |= 1 << ((mmTPC7_QM_CQ_CFG1 & 0x7F) >> 2);
2139 	mask |= 1 << ((mmTPC7_QM_CQ_ARUSER & 0x7F) >> 2);
2140 	mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO & 0x7F) >> 2);
2141 	mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI & 0x7F) >> 2);
2142 	mask |= 1 << ((mmTPC7_QM_CQ_TSIZE & 0x7F) >> 2);
2143 	mask |= 1 << ((mmTPC7_QM_CQ_CTL & 0x7F) >> 2);
2144 	mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
2145 	mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
2146 	mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS & 0x7F) >> 2);
2147 	mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS & 0x7F) >> 2);
2148 	mask |= 1 << ((mmTPC7_QM_CQ_STS0 & 0x7F) >> 2);
2149 	mask |= 1 << ((mmTPC7_QM_CQ_STS1 & 0x7F) >> 2);
2150 	mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2151 	mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2152 	mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2153 	mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2155 	WREG32(pb_addr + word_offset, ~mask);
2159 	mask = 1 << ((mmTPC7_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
2160 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2161 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2162 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2163 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2164 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2165 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2166 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2167 	mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2168 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2169 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2170 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2171 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2172 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2173 	mask |= 1 << ((mmTPC7_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2175 	WREG32(pb_addr + word_offset, ~mask);
2179 	mask = 1 << ((mmTPC7_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
2180 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
2181 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_PROT & 0x7F) >> 2);
2182 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
2183 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
2184 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
2185 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
2186 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
2187 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
2188 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS0 & 0x7F) >> 2);
2189 	mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS1 & 0x7F) >> 2);
2191 	WREG32(pb_addr + word_offset, ~mask);
2195 	mask = 1 << ((mmTPC7_CMDQ_CQ_CFG0 & 0x7F) >> 2);
2196 	mask |= 1 << ((mmTPC7_CMDQ_CQ_CFG1 & 0x7F) >> 2);
2197 	mask |= 1 << ((mmTPC7_CMDQ_CQ_ARUSER & 0x7F) >> 2);
2198 	mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
2199 	mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
2200 	mask |= 1 << ((mmTPC7_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
2201 	mask |= 1 << ((mmTPC7_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
2202 	mask |= 1 << ((mmTPC7_CMDQ_CQ_STS0 & 0x7F) >> 2);
2203 	mask |= 1 << ((mmTPC7_CMDQ_CQ_STS1 & 0x7F) >> 2);
2204 	mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2205 	mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2206 	mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2207 	mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2209 	WREG32(pb_addr + word_offset, ~mask);
2213 	mask = 1 << ((mmTPC7_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
2214 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2215 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2216 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2217 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2218 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2219 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2220 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2221 	mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2222 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2223 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2224 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2225 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2226 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2227 	mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2228 	mask |= 1 << ((mmTPC7_CMDQ_CP_STS & 0x7F) >> 2);
2229 	mask |= 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
2231 	WREG32(pb_addr + word_offset, ~mask);
2236 	mask = 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
2237 	mask |= 1 << ((mmTPC7_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
2238 	mask |= 1 << ((mmTPC7_CMDQ_CP_DBG_0 & 0x7F) >> 2);
2239 	mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
2240 	mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
2242 	WREG32(pb_addr + word_offset, ~mask);
2275 	u32 pb_addr, mask;
2360 	mask = 1 << ((mmTPC_PLL_CLK_RLX_0 & 0x7C) >> 2);
2362 	WREG32(pb_addr + word_offset, mask);
2445 	 * The mask protects the first 512MB
2531 	 * The mask protects the first 512MB
2749 	 * The mask protects the first 512MB
2797 	 * The mask protects the first 512MB
2845 	 * The mask protects the first 512MB
2893 	 * The mask protects the first 512MB
2941 	 * The mask protects the first 512MB
2989 	 * The mask protects the first 512MB
3037 	 * The mask protects the first 512MB
3085 	 * The mask protects the first 512MB

Indexes created Sat May 04 09:44:38 MDT 2024