Lines Matching refs:lbw_rng6_mask
2406 u32 lbw_rng6_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2467 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask);
2576 WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2605 WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2634 WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2663 WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2692 WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2721 WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2769 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2817 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2865 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2913 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2961 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3009 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3057 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3105 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);