Lines Matching refs:goya_pb_set_block
18 static void goya_pb_set_block(struct hl_device *hdev, u64 base)
37 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE);
38 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE);
39 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE);
40 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE);
42 goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE);
43 goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE);
45 goya_pb_set_block(hdev, mmMME1_RTR_BASE);
46 goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE);
47 goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE);
48 goya_pb_set_block(hdev, mmMME2_RTR_BASE);
49 goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE);
50 goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE);
51 goya_pb_set_block(hdev, mmMME3_RTR_BASE);
52 goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE);
53 goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE);
55 goya_pb_set_block(hdev, mmMME4_RTR_BASE);
56 goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE);
57 goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE);
59 goya_pb_set_block(hdev, mmMME5_RTR_BASE);
60 goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE);
61 goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE);
63 goya_pb_set_block(hdev, mmMME6_RTR_BASE);
64 goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE);
65 goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE);
277 goya_pb_set_block(hdev, mmDMA_NRTR_BASE);
278 goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE);
279 goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE);
357 goya_pb_set_block(hdev, mmDMA_CH_0_BASE);
435 goya_pb_set_block(hdev, mmDMA_CH_1_BASE);
513 goya_pb_set_block(hdev, mmDMA_CH_2_BASE);
591 goya_pb_set_block(hdev, mmDMA_CH_3_BASE);
669 goya_pb_set_block(hdev, mmDMA_CH_4_BASE);
677 goya_pb_set_block(hdev, mmTPC0_RD_REGULATOR_BASE);
678 goya_pb_set_block(hdev, mmTPC0_WR_REGULATOR_BASE);
872 goya_pb_set_block(hdev, mmTPC1_RTR_BASE);
873 goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE);
874 goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE);
1068 goya_pb_set_block(hdev, mmTPC2_RTR_BASE);
1069 goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE);
1070 goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE);
1264 goya_pb_set_block(hdev, mmTPC3_RTR_BASE);
1265 goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE);
1266 goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE);
1460 goya_pb_set_block(hdev, mmTPC4_RTR_BASE);
1461 goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE);
1462 goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE);
1656 goya_pb_set_block(hdev, mmTPC5_RTR_BASE);
1657 goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE);
1658 goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE);
1852 goya_pb_set_block(hdev, mmTPC6_RTR_BASE);
1853 goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE);
1854 goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE);
2048 goya_pb_set_block(hdev, mmTPC7_NRTR_BASE);
2049 goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE);
2050 goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE);
2278 goya_pb_set_block(hdev, mmPCI_NRTR_BASE);
2279 goya_pb_set_block(hdev, mmPCI_RD_REGULATOR_BASE);
2280 goya_pb_set_block(hdev, mmPCI_WR_REGULATOR_BASE);
2282 goya_pb_set_block(hdev, mmSRAM_Y0_X0_BANK_BASE);
2283 goya_pb_set_block(hdev, mmSRAM_Y0_X0_RTR_BASE);
2284 goya_pb_set_block(hdev, mmSRAM_Y0_X1_BANK_BASE);
2285 goya_pb_set_block(hdev, mmSRAM_Y0_X1_RTR_BASE);
2286 goya_pb_set_block(hdev, mmSRAM_Y0_X2_BANK_BASE);
2287 goya_pb_set_block(hdev, mmSRAM_Y0_X2_RTR_BASE);
2288 goya_pb_set_block(hdev, mmSRAM_Y0_X3_BANK_BASE);
2289 goya_pb_set_block(hdev, mmSRAM_Y0_X3_RTR_BASE);
2290 goya_pb_set_block(hdev, mmSRAM_Y0_X4_BANK_BASE);
2291 goya_pb_set_block(hdev, mmSRAM_Y0_X4_RTR_BASE);
2293 goya_pb_set_block(hdev, mmSRAM_Y1_X0_BANK_BASE);
2294 goya_pb_set_block(hdev, mmSRAM_Y1_X0_RTR_BASE);
2295 goya_pb_set_block(hdev, mmSRAM_Y1_X1_BANK_BASE);
2296 goya_pb_set_block(hdev, mmSRAM_Y1_X1_RTR_BASE);
2297 goya_pb_set_block(hdev, mmSRAM_Y1_X2_BANK_BASE);
2298 goya_pb_set_block(hdev, mmSRAM_Y1_X2_RTR_BASE);
2299 goya_pb_set_block(hdev, mmSRAM_Y1_X3_BANK_BASE);
2300 goya_pb_set_block(hdev, mmSRAM_Y1_X3_RTR_BASE);
2301 goya_pb_set_block(hdev, mmSRAM_Y1_X4_BANK_BASE);
2302 goya_pb_set_block(hdev, mmSRAM_Y1_X4_RTR_BASE);
2304 goya_pb_set_block(hdev, mmSRAM_Y2_X0_BANK_BASE);
2305 goya_pb_set_block(hdev, mmSRAM_Y2_X0_RTR_BASE);
2306 goya_pb_set_block(hdev, mmSRAM_Y2_X1_BANK_BASE);
2307 goya_pb_set_block(hdev, mmSRAM_Y2_X1_RTR_BASE);
2308 goya_pb_set_block(hdev, mmSRAM_Y2_X2_BANK_BASE);
2309 goya_pb_set_block(hdev, mmSRAM_Y2_X2_RTR_BASE);
2310 goya_pb_set_block(hdev, mmSRAM_Y2_X3_BANK_BASE);
2311 goya_pb_set_block(hdev, mmSRAM_Y2_X3_RTR_BASE);
2312 goya_pb_set_block(hdev, mmSRAM_Y2_X4_BANK_BASE);
2313 goya_pb_set_block(hdev, mmSRAM_Y2_X4_RTR_BASE);
2315 goya_pb_set_block(hdev, mmSRAM_Y3_X0_BANK_BASE);
2316 goya_pb_set_block(hdev, mmSRAM_Y3_X0_RTR_BASE);
2317 goya_pb_set_block(hdev, mmSRAM_Y3_X1_BANK_BASE);
2318 goya_pb_set_block(hdev, mmSRAM_Y3_X1_RTR_BASE);
2319 goya_pb_set_block(hdev, mmSRAM_Y3_X2_BANK_BASE);
2320 goya_pb_set_block(hdev, mmSRAM_Y3_X2_RTR_BASE);
2321 goya_pb_set_block(hdev, mmSRAM_Y3_X3_BANK_BASE);
2322 goya_pb_set_block(hdev, mmSRAM_Y3_X3_RTR_BASE);
2323 goya_pb_set_block(hdev, mmSRAM_Y3_X4_BANK_BASE);
2324 goya_pb_set_block(hdev, mmSRAM_Y3_X4_RTR_BASE);
2326 goya_pb_set_block(hdev, mmSRAM_Y4_X0_BANK_BASE);
2327 goya_pb_set_block(hdev, mmSRAM_Y4_X0_RTR_BASE);
2328 goya_pb_set_block(hdev, mmSRAM_Y4_X1_BANK_BASE);
2329 goya_pb_set_block(hdev, mmSRAM_Y4_X1_RTR_BASE);
2330 goya_pb_set_block(hdev, mmSRAM_Y4_X2_BANK_BASE);
2331 goya_pb_set_block(hdev, mmSRAM_Y4_X2_RTR_BASE);
2332 goya_pb_set_block(hdev, mmSRAM_Y4_X3_BANK_BASE);
2333 goya_pb_set_block(hdev, mmSRAM_Y4_X3_RTR_BASE);
2334 goya_pb_set_block(hdev, mmSRAM_Y4_X4_BANK_BASE);
2335 goya_pb_set_block(hdev, mmSRAM_Y4_X4_RTR_BASE);
2337 goya_pb_set_block(hdev, mmSRAM_Y5_X0_BANK_BASE);
2338 goya_pb_set_block(hdev, mmSRAM_Y5_X0_RTR_BASE);
2339 goya_pb_set_block(hdev, mmSRAM_Y5_X1_BANK_BASE);
2340 goya_pb_set_block(hdev, mmSRAM_Y5_X1_RTR_BASE);
2341 goya_pb_set_block(hdev, mmSRAM_Y5_X2_BANK_BASE);
2342 goya_pb_set_block(hdev, mmSRAM_Y5_X2_RTR_BASE);
2343 goya_pb_set_block(hdev, mmSRAM_Y5_X3_BANK_BASE);
2344 goya_pb_set_block(hdev, mmSRAM_Y5_X3_RTR_BASE);
2345 goya_pb_set_block(hdev, mmSRAM_Y5_X4_BANK_BASE);
2346 goya_pb_set_block(hdev, mmSRAM_Y5_X4_RTR_BASE);
2348 goya_pb_set_block(hdev, mmPCIE_WRAP_BASE);
2349 goya_pb_set_block(hdev, mmPCIE_CORE_BASE);
2350 goya_pb_set_block(hdev, mmPCIE_DB_CFG_BASE);
2351 goya_pb_set_block(hdev, mmPCIE_DB_CMD_BASE);
2352 goya_pb_set_block(hdev, mmPCIE_AUX_BASE);
2353 goya_pb_set_block(hdev, mmPCIE_DB_RSV_BASE);
2354 goya_pb_set_block(hdev, mmPCIE_PHY_BASE);
2355 goya_pb_set_block(hdev, mmTPC0_NRTR_BASE);
2356 goya_pb_set_block(hdev, mmTPC_PLL_BASE);