habanalabs/gaudi2/gaudi2_security.c

2603 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2608 	hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2612 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2630 	hl_secure_block(hdev, glbl_sec, block_array_size);
2631 	hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2638 		hl_unsecure_registers(hdev,
2646 		hl_unsecure_registers(hdev,
2655 		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2662 		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2671 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
2683 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2688 	ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2695 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2706 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
2711 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2775 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2802 		dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2827 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2836 		dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2844 		dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2863 	gaudi2_init_blocks(hdev, &block_ctx);
2871 	gaudi2_init_blocks(hdev, &block_ctx);
2880 	gaudi2_init_blocks(hdev, &block_ctx);
2884 	gaudi2_init_blocks(hdev, &block_ctx);
2888 	gaudi2_init_blocks(hdev, &block_ctx);
2891 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2969 				hdev->asic_prop.fw_security_enabled)
2972 		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2978 		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2983 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2985 	gaudi2_init_lbw_range_registers_secure(hdev);
2988 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
3024 		dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3055 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3064 		dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3072 		dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3091 	gaudi2_init_blocks(hdev, &block_ctx);
3099 	gaudi2_init_blocks(hdev, &block_ctx);
3107 	gaudi2_init_blocks(hdev, &block_ctx);
3110 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3127 		gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3132 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3153 		dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3169 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3180 	rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3181 	rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3187 			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3193 			gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3202  * @hdev: pointer to hl_device structure
3204 static void gaudi2_init_range_registers(struct hl_device *hdev)
3206 	gaudi2_init_lbw_range_registers(hdev);
3207 	gaudi2_init_hbw_range_registers(hdev);
3208 	gaudi2_init_mmu_range_registers(hdev);
3215  * @hdev: pointer to hl_device structure
3221 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3224 	struct asic_fixed_properties *prop = &hdev->asic_prop;
3231 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3237 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3244 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3249 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3258 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3263 	if (!hdev->asic_prop.fw_security_enabled)
3264 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3270 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3277 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3283 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3291 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3299 	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3311 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3317 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3331 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3339 		rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3348 	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3357 	rc |= gaudi2_init_pb_tpc(hdev);
3358 	rc |= gaudi2_init_pb_tpc_arc(hdev);
3362 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3367 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3376 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3384 	rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
3397 	engine_core_intr_reg = (u32) (hdev->asic_prop.engine_core_interrupt_reg_addr - CFG_BASE);
3403 		dev_err(hdev->dev,
3408 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3413 	if (!hdev->asic_prop.fw_security_enabled)
3414 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3420 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3429 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3433 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3438 	if (!hdev->asic_prop.fw_security_enabled) {
3439 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3443 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3450 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3459 	if (!hdev->asic_prop.fw_security_enabled) {
3461 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3468 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3477 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3485 	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3493 	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3496 			NULL, HL_PB_NA, hdev->nic_ports_mask);
3499 	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3504 			hdev->nic_ports_mask);
3507 	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3513 			hdev->nic_ports_mask);
3516 	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3522 			hdev->nic_ports_mask);
3526 	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3534 	rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3541 	rc |= gaudi2_init_pb_sm_objs(hdev);
3549  * @hdev: pointer to hl_device structure
3554 int gaudi2_init_security(struct hl_device *hdev)
3558 	rc = gaudi2_init_protection_bits(hdev);
3562 	gaudi2_init_range_registers(hdev);
3572 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3577 	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3580 	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3584 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3595 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
3603  * @hdev: pointer to hl_device structure
3609 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3611 	struct asic_fixed_properties *prop = &hdev->asic_prop;
3617 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3622 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3629 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3633 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3642 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3644 	if (!hdev->asic_prop.fw_security_enabled)
3645 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3649 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3654 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3658 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3663 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3669 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3679 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3684 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3696 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3702 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3709 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3716 	gaudi2_ack_pb_tpc(hdev);
3720 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3724 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3728 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3731 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3738 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3740 	if (!hdev->asic_prop.fw_security_enabled)
3741 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3745 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3752 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3754 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3756 	if (!hdev->asic_prop.fw_security_enabled) {
3757 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3759 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3764 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3770 	if (!hdev->asic_prop.fw_security_enabled) {
3772 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3778 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3784 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3790 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3796 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3801 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3802 			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3805 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3807 			hdev->nic_ports_mask);
3810 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3812 			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3815 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3817 			hdev->nic_ports_mask);
3821 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3825 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3833 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3869 	dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,