habanalabs/gaudi2/gaudi2_coresight.c

1927 static int gaudi2_coresight_timeout(struct hl_device *hdev, u64 addr,
1933 	if (hdev->pldm)
1939 		hdev,
1947 		dev_err(hdev->dev,
1954 static int gaudi2_unlock_coresight_unit(struct hl_device *hdev,
1961 	rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
1965 		dev_err(hdev->dev,
1972 static int gaudi2_config_stm(struct hl_device *hdev, struct hl_debug_params *params)
1981 		dev_err(hdev->dev, "Invalid register index in STM\n");
1998 	if (hdev->pldm &&  read_reg == 0x0)
2001 	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2013 		if (hdev->pldm)
2026 		frequency = hdev->asic_prop.psoc_timestamp_frequency;
2047 		rc = gaudi2_coresight_timeout(hdev, base_reg + mmSTM_STMTCSR_OFFSET, 23, false);
2049 			dev_err(hdev->dev, "Failed to disable STM on timeout, error %d\n", rc);
2059 static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *params)
2068 		dev_err(hdev->dev, "Invalid register index in ETF\n");
2088 	if (hdev->pldm &&  read_reg == 0x0)
2091 	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2106 	rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, false);
2108 		dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
2113 	rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, true);
2115 		dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n",
2149 static int gaudi2_etr_validate_address(struct hl_device *hdev, u64 addr, u64 size)
2151 	struct asic_fixed_properties *prop = &hdev->asic_prop;
2152 	struct gaudi2_device *gaudi2 = hdev->asic_specific;
2155 		dev_err(hdev->dev, "ETR buffer size %llu overflow\n", size);
2187 		dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
2192 static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx,
2200 	rc = gaudi2_unlock_coresight_unit(hdev, mmPSOC_ETR_BASE);
2215 	rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
2217 		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
2222 	rc = gaudi2_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
2224 		dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
2238 			dev_err(hdev->dev, "ETR buffer size should be bigger than 0\n");
2242 		if (!gaudi2_etr_validate_address(hdev, input->buffer_address, input->buffer_size)) {
2243 			dev_err(hdev->dev, "ETR buffer address is invalid\n");
2257 		if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) {
2300 static int gaudi2_config_funnel(struct hl_device *hdev, struct hl_debug_params *params)
2308 		dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
2327 	if (hdev->pldm && read_reg == 0x0)
2330 	rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2339 static int gaudi2_config_bmon(struct hl_device *hdev, struct hl_debug_params *params)
2346 		dev_err(hdev->dev, "Invalid register index in BMON\n");
2366 	if (hdev->pldm &&  read_reg == 0x0)
2371 	if (hdev->pldm)
2435 static int gaudi2_config_spmu(struct hl_device *hdev, struct hl_debug_params *params)
2449 		dev_err(hdev->dev, "Invalid register index in SPMU\n");
2468 	if (hdev->pldm && read_reg == 0x0)
2478 			dev_err(hdev->dev, "too many event types values for SPMU enable\n");
2486 		if (hdev->pldm)
2519 				dev_err(hdev->dev, "too many events values for SPMU disable\n");
2545 int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
2552 		rc = gaudi2_config_stm(hdev, params);
2555 		rc = gaudi2_config_etf(hdev, params);
2558 		rc = gaudi2_config_etr(hdev, ctx, params);
2561 		rc = gaudi2_config_funnel(hdev, params);
2564 		rc = gaudi2_config_bmon(hdev, params);
2567 		rc = gaudi2_config_spmu(hdev, params);
2573 		dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
2580 void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
2586 	if (!hdev->pldm)
2589 			rc = gaudi2_config_etf(hdev, &params);
2591 				dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
2594 	rc = gaudi2_config_etr(hdev, ctx, &params);
2596 		dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
2600 static int gaudi2_coresight_set_disabled_components(struct hl_device *hdev, u32 unit_count,
2621 			dev_err(hdev->dev, "index is out of range index(%u) >= units_count(%u)\n",
2670 int gaudi2_coresight_init(struct hl_device *hdev)
2672 	struct asic_fixed_properties *prop = &hdev->asic_prop;
2683 	ret = gaudi2_coresight_set_disabled_components(hdev, TPC_ID_SIZE, prop->tpc_enabled_mask,
2686 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for tpc coresight\n");
2691 	ret = gaudi2_coresight_set_disabled_components(hdev, DEC_ID_SIZE,
2694 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for decoder coresight\n");
2699 	ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
2702 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc0 coresight\n");
2706 	ret = gaudi2_coresight_set_disabled_components(hdev, HBM_ID_SIZE, prop->dram_enabled_mask,
2709 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hbm mc1 coresight\n");
2714 	ret = gaudi2_coresight_set_disabled_components(hdev, HMMU_ID_SIZE,
2717 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for hmmu coresight\n");
2722 	ret = gaudi2_coresight_set_disabled_components(hdev, XBAR_EDGE_ID_SIZE,
2725 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for xbar_edge coresight\n");
2730 	ret = gaudi2_coresight_set_disabled_components(hdev, EDMA_ID_SIZE, prop->edma_enabled_mask,
2733 		dev_err(hdev->dev, "Failed to set disabled cs_dbg units for edma coresight\n");