Lines Matching defs:base_reg
1955 const u64 base_reg)
1959 WREG32(base_reg + mmCORESIGHT_UNLOCK_REGISTER_OFFSET, CORESIGHT_UNLOCK);
1961 rc = gaudi2_coresight_timeout(hdev, base_reg + mmCORESIGHT_UNLOCK_STATUS_REGISTER_OFFSET,
1967 base_reg);
1975 u64 base_reg;
1985 base_reg = debug_stm_regs[params->reg_idx];
1990 if (!base_reg)
1997 read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);
2001 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2011 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x80004);
2014 RREG32(base_reg + mmSTM_STMTCSR_OFFSET);
2016 WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 7);
2017 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
2018 WREG32(base_reg + mmSTM_STMHEER_OFFSET, lower_32_bits(input->he_mask));
2019 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
2020 WREG32(base_reg + mmSTM_STMHEER_OFFSET, upper_32_bits(input->he_mask));
2021 WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0x10);
2022 WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
2023 WREG32(base_reg + mmSTM_STMSPER_OFFSET, lower_32_bits(input->sp_mask));
2024 WREG32(base_reg + mmSTM_STMITATBID_OFFSET, input->id);
2025 WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
2029 WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, frequency);
2030 WREG32(base_reg + mmSTM_STMSYNCR_OFFSET, 0x7FF);
2031 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 0x27 | (input->id << 16));
2033 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
2034 WREG32(base_reg + mmSTM_STMHEMCR_OFFSET, 0);
2035 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 1);
2036 WREG32(base_reg + mmSTM_STMHEER_OFFSET, 0);
2037 WREG32(base_reg + mmSTM_STMHETER_OFFSET, 0);
2038 WREG32(base_reg + mmSTM_STMHEBSR_OFFSET, 0);
2039 WREG32(base_reg + mmSTM_STMSPTER_OFFSET, 0);
2040 WREG32(base_reg + mmSTM_STMSPER_OFFSET, 0);
2041 WREG32(base_reg + mmSTM_STMHEMASTR_OFFSET, 0x80);
2042 WREG32(base_reg + mmSTM_STMSPTRIGCSR_OFFSET, 0);
2043 WREG32(base_reg + mmSTM_STMSPSCR_OFFSET, 0);
2044 WREG32(base_reg + mmSTM_STMSPMSCR_OFFSET, 0);
2045 WREG32(base_reg + mmSTM_STMTSFREQR_OFFSET, 0);
2047 rc = gaudi2_coresight_timeout(hdev, base_reg + mmSTM_STMTCSR_OFFSET, 23, false);
2053 WREG32(base_reg + mmSTM_STMTCSR_OFFSET, 4);
2062 u64 base_reg;
2072 base_reg = debug_etf_regs[params->reg_idx];
2077 if (!base_reg)
2087 read_reg = RREG32(base_reg + mmETF_STS_OFFSET);
2091 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2095 val = RREG32(base_reg + mmETF_CTL_OFFSET);
2100 val = RREG32(base_reg + mmETF_FFCR_OFFSET);
2102 WREG32(base_reg + mmETF_FFCR_OFFSET, val);
2104 WREG32(base_reg + mmETF_FFCR_OFFSET, val);
2106 rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, false);
2113 rc = gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, true);
2120 WREG32(base_reg + mmETF_CTL_OFFSET, 0);
2128 val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;
2131 WREG32(base_reg + mmETF_PSCR_OFFSET, val);
2133 WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
2136 WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC);
2137 WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode);
2138 WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001);
2139 WREG32(base_reg + mmETF_CTL_OFFSET, 1);
2141 WREG32(base_reg + mmETF_BUFWM_OFFSET, 0);
2142 WREG32(base_reg + mmETF_MODE_OFFSET, 0);
2143 WREG32(base_reg + mmETF_FFCR_OFFSET, 0);
2302 u64 base_reg;
2312 base_reg = debug_funnel_regs[params->reg_idx];
2317 if (!base_reg)
2326 read_reg = RREG32(base_reg + mmFUNNEL_DEVID_OFFSET);
2330 rc = gaudi2_unlock_coresight_unit(hdev, base_reg);
2334 WREG32(base_reg, val);
2342 u64 base_reg;
2350 base_reg = debug_bmon_regs[params->reg_idx];
2355 if (!base_reg)
2365 read_reg = RREG32(base_reg + mmBMON_CR_OFFSET);
2369 WREG32(base_reg + mmBMON_ATTREN_OFFSET, 1);
2372 RREG32(base_reg + mmBMON_ATTREN_OFFSET);
2376 WREG32(base_reg + mmBMON_RESET_OFFSET, 0x1);
2384 WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, lower_32_bits(input->start_addr0));
2385 WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, upper_32_bits(input->start_addr0));
2386 WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, lower_32_bits(input->addr_mask0));
2387 WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, upper_32_bits(input->addr_mask0));
2388 WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, lower_32_bits(input->start_addr1));
2389 WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, upper_32_bits(input->start_addr1));
2390 WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, lower_32_bits(input->addr_mask1));
2391 WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, upper_32_bits(input->addr_mask1));
2392 WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, lower_32_bits(input->start_addr2));
2393 WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, upper_32_bits(input->start_addr2));
2394 WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, lower_32_bits(input->end_addr2));
2395 WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, upper_32_bits(input->end_addr2));
2396 WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, lower_32_bits(input->start_addr3));
2397 WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, upper_32_bits(input->start_addr3));
2398 WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, lower_32_bits(input->end_addr3));
2399 WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, upper_32_bits(input->end_addr3));
2401 WREG32(base_reg + mmBMON_IDL_OFFSET, 0x0);
2402 WREG32(base_reg + mmBMON_IDH_OFFSET, 0x0);
2404 WREG32(base_reg + mmBMON_ATTREN_OFFSET, 0);
2405 WREG32(base_reg + mmBMON_BW_WIN_OFFSET, input->bw_win);
2406 WREG32(base_reg + mmBMON_WIN_CAPTURE_OFFSET, input->win_capture);
2407 WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0x1 | (13 << 8));
2408 WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (input->id << 8));
2409 WREG32(base_reg + mmBMON_CR_OFFSET, input->control);
2411 WREG32(base_reg + mmBMON_ADDRL_S0_OFFSET, 0);
2412 WREG32(base_reg + mmBMON_ADDRH_S0_OFFSET, 0);
2413 WREG32(base_reg + mmBMON_ADDRL_E0_OFFSET, 0);
2414 WREG32(base_reg + mmBMON_ADDRH_E0_OFFSET, 0);
2415 WREG32(base_reg + mmBMON_ADDRL_S1_OFFSET, 0);
2416 WREG32(base_reg + mmBMON_ADDRH_S1_OFFSET, 0);
2417 WREG32(base_reg + mmBMON_ADDRL_E1_OFFSET, 0);
2418 WREG32(base_reg + mmBMON_ADDRH_E1_OFFSET, 0);
2419 WREG32(base_reg + mmBMON_ADDRL_S2_OFFSET, 0);
2420 WREG32(base_reg + mmBMON_ADDRH_S2_OFFSET, 0);
2421 WREG32(base_reg + mmBMON_ADDRL_E2_OFFSET, 0);
2422 WREG32(base_reg + mmBMON_ADDRH_E2_OFFSET, 0);
2423 WREG32(base_reg + mmBMON_ADDRL_S3_OFFSET, 0);
2424 WREG32(base_reg + mmBMON_ADDRH_S3_OFFSET, 0);
2425 WREG32(base_reg + mmBMON_ADDRL_E3_OFFSET, 0);
2426 WREG32(base_reg + mmBMON_ADDRH_E3_OFFSET, 0);
2427 WREG32(base_reg + mmBMON_REDUCTION_OFFSET, 0);
2428 WREG32(base_reg + mmBMON_STM_TRC_OFFSET, 0x7 | (0xA << 8));
2429 WREG32(base_reg + mmBMON_CR_OFFSET, 0x77 | 0xf << 24);
2443 u64 base_reg;
2453 base_reg = debug_spmu_regs[params->reg_idx];
2458 if (!base_reg)
2467 read_reg = RREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET);
2482 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013046);
2483 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
2487 RREG32(base_reg);
2490 WREG32(base_reg + mmSPMU_PMEVTYPER0_EL0_OFFSET + i * 4,
2493 WREG32(base_reg + mmSPMU_PMTRC_OFFSET, input->pmtrc_val);
2494 WREG32(base_reg + mmSPMU_TRC_CTRL_HOST_OFFSET, input->trc_ctrl_host_val);
2495 WREG32(base_reg + mmSPMU_TRC_EN_HOST_OFFSET, input->trc_en_host_val);
2497 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013041);
2506 WREG32(base_reg + mmSPMU_PMCNTENSET_EL0_OFFSET, event_mask);
2514 WREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET, 0x41013040);
2525 base_reg + mmSPMU_PMEVCNTR0_EL0_OFFSET + (i * 8);
2530 output[overflow_idx] = RREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET);
2531 output[cycle_cnt_idx] = RREG32(base_reg + mmSPMU_PMCCNTR_H_EL0_OFFSET);
2533 output[cycle_cnt_idx] |= RREG32(base_reg + mmSPMU_PMCCNTR_L_EL0_OFFSET);
2536 WREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET, 0);
2539 WREG32(base_reg + mmSPMU_PMTRC_OFFSET, 0x100400);