habanalabs/gaudi2/gaudi2.c

2113 /* Special blocks iterator is currently used to configure security protection bits,
2114  * and read global errors. Most HW blocks are addressable and those who aren't (N/A)-
2127 		/* Skip all PSOC blocks except for PSOC_GLOBAL_CONF */
2130 		/* Skip all CPU blocks except for CPU_IF */
3247 		/* Each ARC scheduler has 2 consecutive DCCM blocks */
3357 	struct user_mapped_block *blocks = gaudi2->mapped_blocks;
3359 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3360 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE0_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3361 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3362 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE1_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3363 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3364 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE2_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3365 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3366 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmDCORE3_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3367 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx++], mmPCIE_DEC0_CMD_BASE, HL_BLOCK_SIZE);
3368 	HL_USR_MAPPED_BLK_INIT(&blocks[start_idx], mmPCIE_DEC1_CMD_BASE, HL_BLOCK_SIZE);
3374 	struct user_mapped_block *blocks = gaudi2->mapped_blocks;
3384 		blocks[i].address = gaudi2_arc_dccm_bases[i];
3385 		blocks[i].size = block_size;
3388 	blocks[NUM_ARC_CPUS].address = mmARC_FARM_ARC0_ACP_ENG_BASE;
3389 	blocks[NUM_ARC_CPUS].size = HL_BLOCK_SIZE;
3391 	blocks[NUM_ARC_CPUS + 1].address = mmARC_FARM_ARC1_ACP_ENG_BASE;
3392 	blocks[NUM_ARC_CPUS + 1].size = HL_BLOCK_SIZE;
3394 	blocks[NUM_ARC_CPUS + 2].address = mmARC_FARM_ARC2_ACP_ENG_BASE;
3395 	blocks[NUM_ARC_CPUS + 2].size = HL_BLOCK_SIZE;
3397 	blocks[NUM_ARC_CPUS + 3].address = mmARC_FARM_ARC3_ACP_ENG_BASE;
3398 	blocks[NUM_ARC_CPUS + 3].size = HL_BLOCK_SIZE;
3400 	blocks[NUM_ARC_CPUS + 4].address = mmDCORE0_MME_QM_ARC_ACP_ENG_BASE;
3401 	blocks[NUM_ARC_CPUS + 4].size = HL_BLOCK_SIZE;
3403 	blocks[NUM_ARC_CPUS + 5].address = mmDCORE1_MME_QM_ARC_ACP_ENG_BASE;
3404 	blocks[NUM_ARC_CPUS + 5].size = HL_BLOCK_SIZE;
3406 	blocks[NUM_ARC_CPUS + 6].address = mmDCORE2_MME_QM_ARC_ACP_ENG_BASE;
3407 	blocks[NUM_ARC_CPUS + 6].size = HL_BLOCK_SIZE;
3409 	blocks[NUM_ARC_CPUS + 7].address = mmDCORE3_MME_QM_ARC_ACP_ENG_BASE;
3410 	blocks[NUM_ARC_CPUS + 7].size = HL_BLOCK_SIZE;
3420 		blocks[umr_start_idx + i].address =
3425 		blocks[umr_start_idx + i].size = HL_BLOCK_SIZE;
3432 		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].size = SM_OBJS_BLOCK_SIZE;
3433 		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].size = HL_BLOCK_SIZE;
3435 		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1)].address =
3438 		blocks[USR_MAPPED_BLK_SM_START_IDX + 2 * (i - 1) + 1].address =
3591 	/* Configure Special blocks */
3603 	/* Configure when to skip Special blocks */
8569 	/* There is a single event per NIC macro, so should check its both QMAN blocks */
10706 	for (i = 0 ; i < cfg_ctx->blocks ; i++)