habanalabs/gaudi/gaudi_coresight.c

394 	u64 base_reg;
403 	base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
405 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
413 		WREG32(base_reg + 0xE80, 0x80004);
414 		WREG32(base_reg + 0xD64, 7);
415 		WREG32(base_reg + 0xD60, 0);
416 		WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
417 		WREG32(base_reg + 0xD60, 1);
418 		WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
419 		WREG32(base_reg + 0xE70, 0x10);
420 		WREG32(base_reg + 0xE60, 0);
421 		WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask));
422 		WREG32(base_reg + 0xEF4, input->id);
423 		WREG32(base_reg + 0xDF4, 0x80);
427 		WREG32(base_reg + 0xE8C, frequency);
428 		WREG32(base_reg + 0xE90, 0x1F00);
431 		if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE &&
432 			(CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) {
434 			WREG32(base_reg + 0xE68, 0xffff8005);
435 			WREG32(base_reg + 0xE6C, 0x0);
438 		WREG32(base_reg + 0xE80, 0x23 | (input->id << 16));
440 		WREG32(base_reg + 0xE80, 4);
441 		WREG32(base_reg + 0xD64, 0);
442 		WREG32(base_reg + 0xD60, 1);
443 		WREG32(base_reg + 0xD00, 0);
444 		WREG32(base_reg + 0xD20, 0);
445 		WREG32(base_reg + 0xD60, 0);
446 		WREG32(base_reg + 0xE20, 0);
447 		WREG32(base_reg + 0xE00, 0);
448 		WREG32(base_reg + 0xDF4, 0x80);
449 		WREG32(base_reg + 0xE70, 0);
450 		WREG32(base_reg + 0xE60, 0);
451 		WREG32(base_reg + 0xE64, 0);
452 		WREG32(base_reg + 0xE8C, 0);
454 		rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
462 		WREG32(base_reg + 0xE80, 4);
472 	u64 base_reg;
481 	base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
483 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
485 	val = RREG32(base_reg + 0x20);
490 	val = RREG32(base_reg + 0x304);
492 	WREG32(base_reg + 0x304, val);
494 	WREG32(base_reg + 0x304, val);
496 	rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false);
504 	rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true);
512 	WREG32(base_reg + 0x20, 0);
520 		WREG32(base_reg + 0x34, 0x3FFC);
521 		WREG32(base_reg + 0x28, input->sink_mode);
522 		WREG32(base_reg + 0x304, 0x4001);
523 		WREG32(base_reg + 0x308, 0xA);
524 		WREG32(base_reg + 0x20, 1);
526 		WREG32(base_reg + 0x34, 0);
527 		WREG32(base_reg + 0x28, 0);
528 		WREG32(base_reg + 0x304, 0);
701 	u64 base_reg;
708 	base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
710 	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
712 	WREG32(base_reg, params->enable ? 0x33F : 0);
721 	u64 base_reg;
728 	base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
730 	WREG32(base_reg + 0x104, 1);
738 		WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
739 		WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
740 		WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
741 		WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
742 		WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
743 		WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
744 		WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
745 		WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
746 		WREG32(base_reg + 0x224, 0);
747 		WREG32(base_reg + 0x234, 0);
748 		WREG32(base_reg + 0x30C, input->bw_win);
749 		WREG32(base_reg + 0x308, input->win_capture);
750 		WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12));
751 		WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12));
752 		WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12));
753 		WREG32(base_reg + 0x100, 0x11);
754 		WREG32(base_reg + 0x304, 0x1);
756 		WREG32(base_reg + 0x200, 0);
757 		WREG32(base_reg + 0x204, 0);
758 		WREG32(base_reg + 0x208, 0xFFFFFFFF);
759 		WREG32(base_reg + 0x20C, 0xFFFFFFFF);
760 		WREG32(base_reg + 0x240, 0);
761 		WREG32(base_reg + 0x244, 0);
762 		WREG32(base_reg + 0x248, 0xFFFFFFFF);
763 		WREG32(base_reg + 0x24C, 0xFFFFFFFF);
764 		WREG32(base_reg + 0x224, 0xFFFFFFFF);
765 		WREG32(base_reg + 0x234, 0x1070F);
766 		WREG32(base_reg + 0x30C, 0);
767 		WREG32(base_reg + 0x308, 0xFFFF);
768 		WREG32(base_reg + 0x700, 0xA000B00);
769 		WREG32(base_reg + 0x708, 0xA000A00);
770 		WREG32(base_reg + 0x70C, 0xA000C00);
771 		WREG32(base_reg + 0x100, 1);
772 		WREG32(base_reg + 0x304, 0);
773 		WREG32(base_reg + 0x104, 0);
782 	u64 base_reg;
796 	base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
816 		WREG32(base_reg + 0xE04, 0x41013046);
817 		WREG32(base_reg + 0xE04, 0x41013040);
820 			WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
823 		WREG32(base_reg + 0xE04, 0x41013041);
824 		WREG32(base_reg + 0xC00, 0x8000003F);
847 		WREG32(base_reg + 0xE04, 0x41013040);
850 			output[i] = RREG32(base_reg + i * 8);
852 		output[overflow_idx] = RREG32(base_reg + 0xCC0);
854 		output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
856 		output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
858 		WREG32(base_reg + 0xCC0, 0);