Lines Matching refs:nic_offset
3146 static void gaudi_init_nic_qman(struct hl_device *hdev, u32 nic_offset,
3173 q_off = nic_offset + qman_id * 4;
3211 WREG32(mmNIC0_QM0_GLBL_ERR_CFG + nic_offset, nic_qm_err_cfg);
3213 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_LO + nic_offset,
3215 WREG32(mmNIC0_QM0_GLBL_ERR_ADDR_HI + nic_offset,
3218 WREG32(mmNIC0_QM0_GLBL_ERR_WDATA + nic_offset,
3222 WREG32(mmNIC0_QM0_ARB_ERR_MSG_EN + nic_offset,
3226 WREG32(mmNIC0_QM0_ARB_SLV_CHOISE_WDT + nic_offset, GAUDI_ARB_WDT_TIMEOUT);
3228 WREG32(mmNIC0_QM0_GLBL_CFG1 + nic_offset, 0);
3229 WREG32(mmNIC0_QM0_GLBL_PROT + nic_offset,
3239 u32 nic_offset = 0;
3256 nic_offset += nic_delta_between_qmans;
3258 nic_offset -= (nic_delta_between_qmans * 2);
3259 nic_offset += nic_delta_between_nics;
3269 gaudi_init_nic_qman(hdev, nic_offset, (i & 0x3),
3274 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, NIC_QMAN_ENABLE);
3276 nic_offset += nic_delta_between_qmans;
3278 nic_offset -= (nic_delta_between_qmans * 2);
3279 nic_offset += nic_delta_between_nics;
3341 u32 nic_mask, nic_offset = 0;
3352 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, 0);
3354 nic_offset += nic_delta_between_qmans;
3356 nic_offset -= (nic_delta_between_qmans * 2);
3357 nic_offset += nic_delta_between_nics;