habanalabs/gaudi/gaudi.c

2554 	u32 q_off, dma_qm_offset;
2576 	q_off = dma_qm_offset + qman_id * 4;
2578 	WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr));
2579 	WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr));
2581 	WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH));
2582 	WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2583 	WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2585 	WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, QMAN_LDMA_SIZE_OFFSET);
2586 	WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2588 	WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2591 	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2592 	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2593 	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2594 	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2595 	WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
2596 	WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
2597 	WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
2598 	WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
2600 	WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
2735 	u32 q_off, dma_qm_offset;
2756 	q_off = dma_qm_offset + qman_id * 4;
2759 		WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off,
2761 		WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off,
2764 		WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH));
2765 		WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0);
2766 		WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0);
2768 		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2770 		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2772 		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2779 		WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2781 		WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2783 		WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2814 	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
2815 	WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
2816 	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
2817 	WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
2821 		WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
2823 		WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
2825 		WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
2827 		WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
2877 	u32 q_off, mme_id;
2889 	q_off = mme_offset + qman_id * 4;
2892 		WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off,
2894 		WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off,
2897 		WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH));
2898 		WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0);
2899 		WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0);
2901 		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2903 		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2905 		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2912 		WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
2914 		WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
2916 		WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
2950 	WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo);
2951 	WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi);
2952 	WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo);
2953 	WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi);
3003 	u32 q_off, tpc_id;
3022 	q_off = tpc_offset + qman_id * 4;
3028 		WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off,
3030 		WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off,
3033 		WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH));
3034 		WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0);
3035 		WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0);
3037 		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3039 		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3041 		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3048 		WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3050 		WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3052 		WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3083 	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3084 	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3085 	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3086 	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3090 		WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off,
3092 		WREG32(mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off,
3094 		WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off,
3096 		WREG32(mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off,
3154 	u32 q_off;
3173 	q_off = nic_offset + qman_id * 4;
3175 	WREG32(mmNIC0_QM0_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_base_addr));
3176 	WREG32(mmNIC0_QM0_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_base_addr));
3178 	WREG32(mmNIC0_QM0_PQ_SIZE_0 + q_off, ilog2(NIC_QMAN_LENGTH));
3179 	WREG32(mmNIC0_QM0_PQ_PI_0 + q_off, 0);
3180 	WREG32(mmNIC0_QM0_PQ_CI_0 + q_off, 0);
3182 	WREG32(mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 + q_off,
3184 	WREG32(mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off,
3186 	WREG32(mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off,
3189 	WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo);
3190 	WREG32(mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi);
3191 	WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo);
3192 	WREG32(mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi);
3195 	WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo);
3196 	WREG32(mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi);
3197 	WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
3198 	WREG32(mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
4191 	u32 db_reg_offset, db_value, dma_qm_offset, q_off, irq_handler_offset;
4200 		q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4201 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4207 		q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4;
4208 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4214 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4215 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4221 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4222 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4228 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4229 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4235 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4236 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4242 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4243 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4249 		q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4;
4250 		db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off;
4424 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4425 		db_reg_offset = mmNIC0_QM0_PQ_PI_0 + q_off;
4432 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4433 		db_reg_offset = mmNIC0_QM1_PQ_PI_0 + q_off;
4440 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4441 		db_reg_offset = mmNIC1_QM0_PQ_PI_0 + q_off;
4448 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4449 		db_reg_offset = mmNIC1_QM1_PQ_PI_0 + q_off;
4456 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4457 		db_reg_offset = mmNIC2_QM0_PQ_PI_0 + q_off;
4464 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4465 		db_reg_offset = mmNIC2_QM1_PQ_PI_0 + q_off;
4472 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4473 		db_reg_offset = mmNIC3_QM0_PQ_PI_0 + q_off;
4480 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4481 		db_reg_offset = mmNIC3_QM1_PQ_PI_0 + q_off;
4488 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4489 		db_reg_offset = mmNIC4_QM0_PQ_PI_0 + q_off;
4496 		q_off = ((hw_queue_id - 1) & 0x3) * 4;
4497 		db_reg_offset = mmNIC4_QM1_PQ_PI_0 + q_off;