habanalabs/gaudi/gaudi.c

2643 	u32 dma_offset = dma_id * DMA_CORE_OFFSET;
2647 	WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0);
2648 	WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0);
2651 	WREG32(mmDMA0_CORE_LBW_MAX_OUTSTAND + dma_offset, 15);
2657 	WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg);
2663 	WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset,
2665 	WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset,
2668 	WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset,
2670 	WREG32(mmDMA0_CORE_PROT + dma_offset,
2673 	WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset,
2675 	WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT);
4570 			u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4579 			WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset,
4581 			WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset,
4583 			WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset,
4585 			WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset,
4587 			WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset,
4589 			WREG32(mmDMA0_CORE_COMMIT + dma_offset,
4600 			u32 dma_offset = dma_id * DMA_CORE_OFFSET;
4604 				mmDMA0_CORE_STS0 + dma_offset,
5797 		u32 dma_offset = i * DMA_CORE_OFFSET;
5799 		WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset,
5801 		WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset,
5803 		WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001);
5809 			WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset,
5882 	u64 dma_offset;
5885 	dma_offset = dma_id * DMA_CORE_OFFSET;
5887 	WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, lower_32_bits(addr));
5888 	WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, upper_32_bits(addr));
5889 	WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(dma_addr));
5890 	WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, upper_32_bits(dma_addr));
5891 	WREG32(mmDMA0_CORE_DST_TSIZE_0 + dma_offset, size_to_dma);
5892 	WREG32(mmDMA0_CORE_COMMIT + dma_offset,
5897 		mmDMA0_CORE_STS0 + dma_offset,
5911 	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
5917 		WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
5930 	u64 dma_offset, qm_offset;
5944 	dma_offset = dma_id * DMA_CORE_OFFSET;
5946 	dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
5954 		dma_offset = dma_id * DMA_CORE_OFFSET;
5956 		dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);
5978 	WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT));
5981 	err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);
5986 		WREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset, err_cause);
6017 	WREG32_AND(mmDMA0_CORE_PROT + dma_offset,
6357 	u32 tmp, timeout, dma_offset;
6385 	dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET;
6387 	WREG32(mmDMA0_CORE_PROT + dma_offset,
6409 	WREG32(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_ERR_VAL_SHIFT));
6435 	u32 dma_id[2], dma_offset, err_cause[2], mask, i;
6466 		dma_offset = dma_id[i] * DMA_CORE_OFFSET;
6467 		err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);