include/variant/tie-asm.h

60       *      ptr         Save area pointer address register (clobbered)
67       *      ofs         Offset from start of larger sequence (from value of first ptr
76     .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
80 	xchal_sa_align	\ptr, 0, 1020, 4, 4
82 	s32i	\at1, \ptr, .Lxchal_ofs_+0
85 	xchal_sa_align	\ptr, 0, 1020, 4, 4
90 	xchal_sa_align	\ptr, 0, 1016, 4, 4
92 	s32i	\at1, \ptr, .Lxchal_ofs_+0
94 	s32i	\at1, \ptr, .Lxchal_ofs_+4
97 	xchal_sa_align	\ptr, 0, 1016, 4, 4
102 	xchal_sa_align	\ptr, 0, 1000, 4, 4
104 	s32i	\at1, \ptr, .Lxchal_ofs_+0
106 	s32i	\at1, \ptr, .Lxchal_ofs_+4
108 	s32i	\at1, \ptr, .Lxchal_ofs_+8
110 	s32i	\at1, \ptr, .Lxchal_ofs_+12
112 	s32i	\at1, \ptr, .Lxchal_ofs_+16
114 	s32i	\at1, \ptr, .Lxchal_ofs_+20
117 	xchal_sa_align	\ptr, 0, 1000, 4, 4
126       *      ptr         Save area pointer address register (clobbered)
133       *      ofs         Offset from start of larger sequence (from value of first ptr
142     .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
146 	xchal_sa_align	\ptr, 0, 1020, 4, 4
147 	l32i	\at1, \ptr, .Lxchal_ofs_+0
151 	xchal_sa_align	\ptr, 0, 1020, 4, 4
156 	xchal_sa_align	\ptr, 0, 1016, 4, 4
157 	l32i	\at1, \ptr, .Lxchal_ofs_+0
159 	l32i	\at1, \ptr, .Lxchal_ofs_+4
163 	xchal_sa_align	\ptr, 0, 1016, 4, 4
168 	xchal_sa_align	\ptr, 0, 1000, 4, 4
169 	l32i	\at1, \ptr, .Lxchal_ofs_+0
171 	l32i	\at1, \ptr, .Lxchal_ofs_+4
173 	l32i	\at1, \ptr, .Lxchal_ofs_+8
175 	l32i	\at1, \ptr, .Lxchal_ofs_+12
177 	l32i	\at1, \ptr, .Lxchal_ofs_+16
179 	l32i	\at1, \ptr, .Lxchal_ofs_+20
183 	xchal_sa_align	\ptr, 0, 1000, 4, 4
194      *      ptr         Save area pointer address register (clobbered)
201     .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
205 	xchal_sa_align	\ptr, 0, 0, 8, 8
207 	s32i	\at1, \ptr, .Lxchal_ofs_+0
209 	s32i	\at1, \ptr, .Lxchal_ofs_+4
211 	s32i	\at1, \ptr, .Lxchal_ofs_+8
213 	s32i	\at1, \ptr, .Lxchal_ofs_+12
215 	s32i	\at1, \ptr, .Lxchal_ofs_+16
217 	s32i	\at1, \ptr, .Lxchal_ofs_+20
218 	ae_sp24x2s.i	aep0, \ptr, .Lxchal_ofs_+24
219 	ae_sp24x2s.i	aep1, \ptr, .Lxchal_ofs_+32
220 	ae_sp24x2s.i	aep2, \ptr, .Lxchal_ofs_+40
221 	ae_sp24x2s.i	aep3, \ptr, .Lxchal_ofs_+48
222 	ae_sp24x2s.i	aep4, \ptr, .Lxchal_ofs_+56
223 	addi	\ptr, \ptr, 64
224 	ae_sp24x2s.i	aep5, \ptr, .Lxchal_ofs_+0
225 	ae_sp24x2s.i	aep6, \ptr, .Lxchal_ofs_+8
226 	ae_sp24x2s.i	aep7, \ptr, .Lxchal_ofs_+16
227 	ae_sq56s.i	aeq0, \ptr, .Lxchal_ofs_+24
228 	ae_sq56s.i	aeq1, \ptr, .Lxchal_ofs_+32
229 	ae_sq56s.i	aeq2, \ptr, .Lxchal_ofs_+40
230 	ae_sq56s.i	aeq3, \ptr, .Lxchal_ofs_+48
234 	xchal_sa_align	\ptr, 0, 0, 8, 8
242      *      ptr         Save area pointer address register (clobbered)
249     .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
253 	xchal_sa_align	\ptr, 0, 0, 8, 8
254 	l32i	\at1, \ptr, .Lxchal_ofs_+0
256 	l32i	\at1, \ptr, .Lxchal_ofs_+4
258 	l32i	\at1, \ptr, .Lxchal_ofs_+8
260 	l32i	\at1, \ptr, .Lxchal_ofs_+12
262 	l32i	\at1, \ptr, .Lxchal_ofs_+16
264 	l32i	\at1, \ptr, .Lxchal_ofs_+20
266 	ae_lp24x2.i	aep0, \ptr, .Lxchal_ofs_+24
267 	ae_lp24x2.i	aep1, \ptr, .Lxchal_ofs_+32
268 	ae_lp24x2.i	aep2, \ptr, .Lxchal_ofs_+40
269 	ae_lp24x2.i	aep3, \ptr, .Lxchal_ofs_+48
270 	ae_lp24x2.i	aep4, \ptr, .Lxchal_ofs_+56
271 	addi	\ptr, \ptr, 64
272 	ae_lp24x2.i	aep5, \ptr, .Lxchal_ofs_+0
273 	ae_lp24x2.i	aep6, \ptr, .Lxchal_ofs_+8
274 	ae_lp24x2.i	aep7, \ptr, .Lxchal_ofs_+16
275 	addi	\ptr, \ptr, 24
276 	ae_lq56.i	aeq0, \ptr, .Lxchal_ofs_+0
277 	ae_lq56.i	aeq1, \ptr, .Lxchal_ofs_+8
278 	ae_lq56.i	aeq2, \ptr, .Lxchal_ofs_+16
279 	ae_lq56.i	aeq3, \ptr, .Lxchal_ofs_+24
283 	xchal_sa_align	\ptr, 0, 0, 8, 8