Lines Matching refs:idx
135 static inline uint32_t xtensa_pmu_read_counter(int idx)
137 return get_er(XTENSA_PMU_PM(idx));
140 static inline void xtensa_pmu_write_counter(int idx, uint32_t v)
142 set_er(v, XTENSA_PMU_PM(idx));
146 struct hw_perf_event *hwc, int idx)
153 new_raw_count = xtensa_pmu_read_counter(event->hw.idx);
164 struct hw_perf_event *hwc, int idx)
191 xtensa_pmu_write_counter(idx, -left);
252 int idx = hwc->idx;
254 if (WARN_ON_ONCE(idx == -1))
259 xtensa_perf_event_set_period(event, hwc, idx);
264 set_er(hwc->config, XTENSA_PMU_PMCTRL(idx));
270 int idx = hwc->idx;
273 set_er(0, XTENSA_PMU_PMCTRL(idx));
274 set_er(get_er(XTENSA_PMU_PMSTAT(idx)),
275 XTENSA_PMU_PMSTAT(idx));
281 xtensa_perf_event_update(event, &event->hw, idx);
294 int idx = hwc->idx;
296 if (__test_and_set_bit(idx, ev->used_mask)) {
297 idx = find_first_zero_bit(ev->used_mask,
299 if (idx == XCHAL_NUM_PERF_COUNTERS)
302 __set_bit(idx, ev->used_mask);
303 hwc->idx = idx;
305 ev->event[idx] = event;
321 __clear_bit(event->hw.idx, ev->used_mask);
327 xtensa_perf_event_update(event, &event->hw, event->hw.idx);