x86/power/cpu.c

39 static void msr_save_context(struct saved_context *ctxt)
41 	struct saved_msr *msr = ctxt->saved_msrs.array;
42 	struct saved_msr *end = msr + ctxt->saved_msrs.num;
51 static void msr_restore_context(struct saved_context *ctxt)
53 	struct saved_msr *msr = ctxt->saved_msrs.array;
54 	struct saved_msr *end = msr + ctxt->saved_msrs.num;
67  * @ctxt: Structure to store the registers contents in.
79 static void __save_processor_state(struct saved_context *ctxt)
89 	store_idt(&ctxt->idt);
97 	ctxt->gdt_desc.size = GDT_SIZE - 1;
98 	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
100 	store_tr(ctxt->tr);
106 	savesegment(gs, ctxt->gs);
108 	savesegment(fs, ctxt->fs);
109 	savesegment(ds, ctxt->ds);
110 	savesegment(es, ctxt->es);
112 	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
113 	rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
114 	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
117 	rdmsrl(MSR_EFER, ctxt->efer);
123 	ctxt->cr0 = read_cr0();
124 	ctxt->cr2 = read_cr2();
125 	ctxt->cr3 = __read_cr3();
126 	ctxt->cr4 = __read_cr4();
127 	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
128 					       &ctxt->misc_enable);
129 	msr_save_context(ctxt);
190  * @ctxt: Structure to load the registers contents from.
195 static void notrace __restore_processor_state(struct saved_context *ctxt)
199 	if (ctxt->misc_enable_saved)
200 		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
206 	if (ctxt->cr4)
207 		__write_cr4(ctxt->cr4);
210 	wrmsrl(MSR_EFER, ctxt->efer);
211 	__write_cr4(ctxt->cr4);
213 	write_cr3(ctxt->cr3);
214 	write_cr2(ctxt->cr2);
215 	write_cr0(ctxt->cr0);
218 	load_idt(&ctxt->idt);
233 	wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
246 	loadsegment(ds, ctxt->es);
247 	loadsegment(es, ctxt->es);
248 	loadsegment(fs, ctxt->fs);
249 	load_gs_index(ctxt->gs);
256 	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
257 	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
259 	loadsegment(gs, ctxt->gs);
278 	msr_restore_context(ctxt);