platform/intel-quark/imr.c

3  * imr.c -- Intel Isolated Memory Region driver
30 #include <asm/imr.h>
89  * @imr:	pointer to IMR descriptor.
92 static inline int imr_is_enabled(struct imr_regs *imr)
94 	return !(imr->rmask == IMR_READ_ACCESS_ALL &&
95 		 imr->wmask == IMR_WRITE_ACCESS_ALL &&
96 		 imr_to_phys(imr->addr_lo) == 0 &&
97 		 imr_to_phys(imr->addr_hi) == 0);
103  * Requires caller to hold imr mutex.
107  * @imr:	IMR structure representing address and access masks.
110 static int imr_read(struct imr_device *idev, u32 imr_id, struct imr_regs *imr)
115 	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_lo);
119 	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_hi);
123 	ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->rmask);
127 	return iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->wmask);
133  * Requires caller to hold imr mutex.
138  * @imr:	IMR structure representing address and access masks.
141 static int imr_write(struct imr_device *idev, u32 imr_id, struct imr_regs *imr)
149 	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_lo);
153 	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_hi);
157 	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->rmask);
161 	ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->wmask);
175 	     imr_to_phys(imr->addr_lo), imr_to_phys(imr->addr_hi) + IMR_MASK);
193 	struct imr_regs imr;
201 		ret = imr_read(idev, i, &imr);
210 		if (imr_is_enabled(&imr)) {
211 			base = imr_to_phys(imr.addr_lo);
212 			end = imr_to_phys(imr.addr_hi) + IMR_MASK;
219 		seq_printf(s, "imr%02i: base=%pa, end=%pa, size=0x%08zx "
221 			   &base, &end, size, imr.rmask, imr.wmask,
222 			   imr_is_enabled(&imr) ? "enabled " : "disabled",
223 			   imr.addr_lo & IMR_LOCK ? "locked" : "unlocked");
281  * @imr:	imr being checked.
284 static inline int imr_address_overlap(phys_addr_t addr, struct imr_regs *imr)
286 	return addr >= imr_to_phys(imr->addr_lo) && addr <= imr_to_phys(imr->addr_hi);
304 	struct imr_regs imr;
324 	imr.addr_lo = phys_to_imr(base);
325 	imr.addr_hi = phys_to_imr(end);
326 	imr.rmask = rmask;
327 	imr.wmask = wmask;
328 	if (!imr_is_enabled(&imr))
341 		ret = imr_read(idev, i, &imr);
347 		if (imr_is_enabled(&imr)) {
348 			if (imr_address_overlap(base, &imr))
350 			if (imr_address_overlap(end, &imr))
367 	imr.addr_lo = phys_to_imr(base);
368 	imr.addr_hi = phys_to_imr(end);
369 	imr.rmask = rmask;
370 	imr.wmask = wmask;
372 	ret = imr_write(idev, reg, &imr);
379 		imr.addr_lo = 0;
380 		imr.addr_hi = 0;
381 		imr.rmask = IMR_READ_ACCESS_ALL;
382 		imr.wmask = IMR_WRITE_ACCESS_ALL;
383 		imr_write(idev, reg, &imr);
400  * @reg:	imr index to remove.
413 	struct imr_regs imr;
438 		ret = imr_read(idev, reg, &imr);
442 		if (!imr_is_enabled(&imr) || imr.addr_lo & IMR_LOCK) {
450 			ret = imr_read(idev, i, &imr);
454 			if (!imr_is_enabled(&imr) || imr.addr_lo & IMR_LOCK)
457 			if ((imr_to_phys(imr.addr_lo) == base) &&
458 			    (imr_to_phys(imr.addr_hi) == end)) {
474 	imr.addr_lo = 0;
475 	imr.addr_hi = 0;
476 	imr.rmask = IMR_READ_ACCESS_ALL;
477 	imr.wmask = IMR_WRITE_ACCESS_ALL;
479 	ret = imr_write(idev, reg, &imr);
513  * @reg:	imr index to remove.