Lines Matching defs:b2
41 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
42 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
43 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
47 #define EMIT2_off32(b1, b2, off) \
48 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
49 #define EMIT3_off32(b1, b2, b3, off) \
50 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
51 #define EMIT4_off32(b1, b2, b3, b4, off) \
52 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
780 u8 b1, b2, b3;
789 b2 = 0xC7;
791 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
802 b2 = 0x31; /* xor */
804 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
1271 u8 b1, b2;
1296 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
1298 EMIT3(b0, b1, b2);
1378 u8 b2 = 0, b3 = 0;
1400 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1401 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1481 * b3 holds 'normal' opcode, b2 short form only valid
1487 b2 = 0x05;
1491 b2 = 0x2D;
1495 b2 = 0x25;
1499 b2 = 0x0D;
1503 b2 = 0x35;
1510 EMIT1_off32(b2, imm32);