Lines Matching defs:cache
22 * additional cache attribute logic.
25 * cache attribute information to the mapped memory range: there's 3 bits used,
27 * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT).
192 enum page_cache_mode cache;
196 case PAT_UC: cache = CM(UC); cache_mode = "UC "; break;
197 case PAT_WC: cache = CM(WC); cache_mode = "WC "; break;
198 case PAT_WT: cache = CM(WT); cache_mode = "WT "; break;
199 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break;
200 case PAT_WB: cache = CM(WB); cache_mode = "WB "; break;
201 case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break;
202 default: cache = CM(WB); cache_mode = "WB "; break;
207 return cache;
213 * Update the cache mode to pgprot translation tables according to PAT
219 enum page_cache_mode cache;
225 cache = pat_get_cache_mode((pat >> (i * 8)) & 7,
227 update_cache_mode_entry(i, cache);
251 * value to enable additional cache attributes, WC, WT and WP.
279 * cache bits, PWT (Write Through) and PCD (Cache Disable).
299 * Xen PV doesn't allow to set PAT MSR, but all cache modes are
798 /* This check is needed to avoid cache aliasing when PAT is enabled */
1098 * to the same pfn & cache type with VM_PAT set.