x86/kvm/x86.c

165  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
640 /* Forcibly leave the nested mode in cases like a vCPU reset */
1283 	 * Do not condition the GPA check on long mode, this helper is used to
1285 	 * the current vCPU mode is accurate.
2148 	return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2509 static inline bool gtod_is_based_on_tsc(int mode)
2511 	return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2826 			  int *mode)
2836 			*mode = VDSO_CLOCKMODE_HVCLOCK;
2841 			*mode = VDSO_CLOCKMODE_NONE;
2845 		*mode = VDSO_CLOCKMODE_TSC;
2851 		*mode = VDSO_CLOCKMODE_NONE;
2854 	if (*mode == VDSO_CLOCKMODE_NONE)
2868 	int mode;
2874 		ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2880 	return mode;
2891 	int mode;
2897 		ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2903 	return mode;
2910 	int mode;
2917 		ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2924 	return mode;
4761 		 * so do not report SMM to be available if real mode is
4762 		 * emulated via vm86 mode.  Still, do not go to great lengths
5375 	 * In guest mode, payload delivery should be deferred if the exception
7958 		if (ctxt->mode != X86EMUL_MODE_PROT64)
8676 	ctxt->mode = (!is_protmode(vcpu))		? X86EMUL_MODE_REAL :
9187 		if (ctxt->mode != X86EMUL_MODE_PROT64)
9925 	 * When tsc is in permanent catchup mode guests won't be able to use
10610 	 * despite being in x2APIC mode.  For simplicity, inhibiting the APIC
10937 	/* Store vcpu->apicv_active before vcpu->mode.  */
10938 	smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10943 	 * 1) We should set ->mode before checking ->requests.  Please see
10946 	 * 2) For APICv, we should set ->mode before checking PID.ON. This
10950 	 * 3) This also orders the write to mode from any reads to the page
10967 		vcpu->mode = OUTSIDE_GUEST_MODE;
11050 	vcpu->mode = OUTSIDE_GUEST_MODE;
11129 		 * hypervisor timer runs only when the CPU is in guest mode.
11712 		 * 64-bit mode (though maybe in a 32-bit code segment).
11721 		 * Not in 64-bit mode: EFER.LMA is clear and the code
12462 	 * catchup mode.  This will catchup all VCPUs to real time, but cannot
13313 		 * The real mode IDT in particular is unlikely to have a #PF
13496 	 * remapped mode, so we can re-use the current implementation