x86/kvm/lapic.c

166 	return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
259 	 * vCPU is in legacy xAPIC mode, and silently ignore aliased xAPIC IDs
327 	 * To optimize logical mode delivery, all software-enabled APICs must
328 	 * be configured for the same mode.
338 	 * In x2APIC mode, the LDR is read-only and derived directly from the
340 	 * kvm_apic_map.phys_map to optimize logical mode x2APIC interrupts by
619 	[LVT_TIMER] = LVT_MASK,      /* timer mode mask added at runtime */
1002 	 * Hotplug hack: Accept interrupts for vCPUs in xAPIC mode as if they
1003 	 * were in x2APIC mode if the target APIC ID can't be encoded as an
1005 	 * start in xAPIC mode) with an APIC ID that is unaddressable in xAPIC
1006 	 * mode.  Match the x2APIC ID if and only if the target APIC ID can't
1045  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
1249  * This routine tries to handle interrupts in posted mode, here is how
1251  * - For single-destination interrupts, handle it in posted mode
1253  *   interrupt, handle it in posted mode and use the following mechanism
1260  * - Otherwise, use remapped mode to inject the interrupt.
1384 		printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1638 	/* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */
1655 	 * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in
2770 	int vector, mode, trig_mode;
2775 		mode = reg & APIC_MODE_MASK;
2778 		r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
2934 	 * on exit" mode.  Then we cannot inject the interrupt via RVI,
2979 		 * In x2APIC mode, the LDR is fixed and based on the id.  And
3213 	 * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
3307 		 * are blocked as a result of transitioning to VMX root mode.
3313 	 * mode, SVM with GIF=0), while SIPIs are dropped if the CPU isn't in