Lines Matching defs:which
78 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
134 * Read the SPEC_CTRL MSR to account for reserved bits which may
340 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
351 * TSX is enabled, select alternate mitigation for TAA which is
634 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
891 * On CPUs which are vulnerable to Meltdown, SMAP does not
916 * GS, in which case SMAP provides no protection.
1378 * injection in user-mode as the IBRS bit remains always set which
1797 * across context switches, for which the CALLs/RETs may be unbalanced.
1803 * which could have a user-poisoned BTB or BHB entry.
1906 * Enable the idle clearing if SMT is active on CPUs which are
2218 * call. Currently, this is possible on an AMD CPU which has the
2257 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
2260 switch (which) {
2338 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2340 switch (which) {
2381 * address bit due to memory holes, which has been observed on machines
2382 * which report 36bits physical address bits and have 32G RAM installed,