events/intel/uncore_nhmex.c

353 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
368 		reg1->reg = NHMEX_B0_MSR_MATCH;
370 		reg1->reg = NHMEX_B1_MSR_MATCH;
371 	reg1->idx = 0;
372 	reg1->config = event->attr.config1;
380 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
383 	if (reg1->idx != EXTRA_REG_NONE) {
384 		wrmsrl(reg1->reg, reg1->config);
385 		wrmsrl(reg1->reg + 1, reg2->config);
444 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
453 		reg1->reg = NHMEX_S0_MSR_MM_CFG;
455 		reg1->reg = NHMEX_S1_MSR_MM_CFG;
456 	reg1->idx = 0;
457 	reg1->config = event->attr.config1;
465 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
468 	if (reg1->idx != EXTRA_REG_NONE) {
469 		wrmsrl(reg1->reg, 0);
470 		wrmsrl(reg1->reg + 1, reg1->config);
471 		wrmsrl(reg1->reg + 2, reg2->config);
472 		wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
632 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
633 	u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
634 	u64 config = reg1->config;
652 		config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
654 		config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
655 	config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
662 		reg1->config = config;
663 		reg1->idx = ~0xff | new_idx;
671 	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
674 	u64 config1 = reg1->config;
676 	idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
677 	idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
680 		if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
705 		if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
707 		reg1->alloc |= alloc;
721 		BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
725 		if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
740 	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
746 	if (reg1->alloc & 0x1)
747 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
748 	if (reg1->alloc & 0x2)
749 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
750 	reg1->alloc = 0;
768 	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
794 		reg1->idx &= ~(0xff << (reg_idx * 8));
795 		reg1->reg &= ~(0xffff << (reg_idx * 16));
796 		reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
797 		reg1->reg |= msr << (reg_idx * 16);
798 		reg1->config = event->attr.config1;
838 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
842 	idx = __BITS_VALUE(reg1->idx, 0, 8);
844 		wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
846 	idx = __BITS_VALUE(reg1->idx, 1, 8);
848 		wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
947 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
950 	if (reg1->idx % 2) {
951 		reg1->idx--;
954 		reg1->idx++;
959 	switch (reg1->idx % 6) {
962 		reg1->config >>= 8;
966 		reg1->config <<= 8;
981 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
989 	if (!uncore_box_is_fake(box) && reg1->alloc)
992 	idx = reg1->idx % 6;
993 	config1 = reg1->config;
999 	er_idx += (reg1->idx / 6) * 5;
1004 		if (!atomic_read(&er->ref) || er->config == reg1->config) {
1006 			er->config = reg1->config;
1025 				 er->config1 == reg1->config &&
1029 			er->config1 = reg1->config;
1044 		if (idx != reg1->idx % 6) {
1053 			if (idx != reg1->idx % 6)
1055 			reg1->alloc = 1;
1065 	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1068 	if (uncore_box_is_fake(box) || !reg1->alloc)
1071 	idx = reg1->idx % 6;
1075 	er_idx += (reg1->idx / 6) * 5;
1083 	reg1->alloc = 0;
1089 	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1098 	reg1->idx = idx;
1099 	reg1->config = event->attr.config1;
1114 	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1118 	idx = reg1->idx;
1123 		wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
1126 		wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
1136 		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
1142 		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);