events/intel/uncore_nhmex.c

555 	struct intel_uncore_extra_reg *er;
561 		er = &box->shared_regs[idx];
562 		raw_spin_lock_irqsave(&er->lock, flags);
563 		if (!atomic_read(&er->ref) || er->config == config) {
564 			atomic_inc(&er->ref);
565 			er->config = config;
568 		raw_spin_unlock_irqrestore(&er->lock, flags);
586 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
588 	raw_spin_lock_irqsave(&er->lock, flags);
590 	if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
597 	if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
598 		atomic_add(1 << (idx * 8), &er->ref);
605 		er->config &= ~mask;
606 		er->config |= (config & mask);
609 	raw_spin_unlock_irqrestore(&er->lock, flags);
616 	struct intel_uncore_extra_reg *er;
619 		er = &box->shared_regs[idx];
620 		atomic_dec(&er->ref);
625 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
626 	atomic_sub(1 << (idx * 8), &er->ref);
758 static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
760 	if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
761 		return er->idx;
762 	return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
770 	struct extra_reg *er;
778 	for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
779 		if (er->event != (event->hw.config & er->config_mask))
781 		if (event->attr.config1 & ~er->valid_mask)
784 		msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
785 		if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
789 		if (er->idx == EXTRA_REG_NHMEX_M_PLD)
796 		reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
821 	struct intel_uncore_extra_reg *er;
828 	er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
829 	raw_spin_lock_irqsave(&er->lock, flags);
830 	config = er->config;
831 	raw_spin_unlock_irqrestore(&er->lock, flags);
983 	struct intel_uncore_extra_reg *er;
1001 	er = &box->shared_regs[er_idx];
1002 	raw_spin_lock_irqsave(&er->lock, flags);
1004 		if (!atomic_read(&er->ref) || er->config == reg1->config) {
1005 			atomic_inc(&er->ref);
1006 			er->config = reg1->config;
1015 		if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
1016 				!((er->config ^ config1) & mask)) {
1017 			atomic_add(1 << ((idx - 2) * 8), &er->ref);
1018 			er->config &= ~mask;
1019 			er->config |= config1 & mask;
1023 		if (!atomic_read(&er->ref) ||
1024 				(er->config == (hwc->config >> 32) &&
1025 				 er->config1 == reg1->config &&
1026 				 er->config2 == reg2->config)) {
1027 			atomic_inc(&er->ref);
1028 			er->config = (hwc->config >> 32);
1029 			er->config1 = reg1->config;
1030 			er->config2 = reg2->config;
1034 	raw_spin_unlock_irqrestore(&er->lock, flags);
1064 	struct intel_uncore_extra_reg *er;
1077 	er = &box->shared_regs[er_idx];
1079 		atomic_sub(1 << ((idx - 2) * 8), &er->ref);
1081 		atomic_dec(&er->ref);