Lines Matching defs:hwc
208 struct hw_perf_event *hwc = &event->hw;
226 hwc->conf = event->attr.config;
227 hwc->conf1 = event->attr.config1;
240 struct hw_perf_event *hwc = &ev->hw;
241 u8 bank = hwc->iommu_bank;
242 u8 cntr = hwc->iommu_cntr;
245 reg = GET_CSOURCE(hwc);
248 reg = GET_DEVID_MASK(hwc);
249 reg = GET_DEVID(hwc) | (reg << 32);
254 reg = GET_PASID_MASK(hwc);
255 reg = GET_PASID(hwc) | (reg << 32);
260 reg = GET_DOMID_MASK(hwc);
261 reg = GET_DOMID(hwc) | (reg << 32);
270 struct hw_perf_event *hwc = &event->hw;
273 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
279 struct hw_perf_event *hwc = &event->hw;
281 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
284 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
285 hwc->state = 0;
302 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
312 struct hw_perf_event *hwc = &event->hw;
315 if (amd_iommu_pc_get_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
331 struct hw_perf_event *hwc = &event->hw;
333 if (hwc->state & PERF_HES_UPTODATE)
341 hwc->state |= PERF_HES_UPTODATE;
344 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
345 hwc->state |= PERF_HES_STOPPED;
367 struct hw_perf_event *hwc = &event->hw;
375 hwc->iommu_bank, hwc->iommu_cntr);