events/amd/ibs.c

101 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
103 	s64 left = local64_read(&hwc->period_left);
104 	s64 period = hwc->sample_period;
112 		local64_set(&hwc->period_left, left);
113 		hwc->last_period = period;
119 		local64_set(&hwc->period_left, left);
120 		hwc->last_period = period;
146 	struct hw_perf_event *hwc = &event->hw;
158 	prev_raw_count = local64_read(&hwc->prev_count);
159 	if (!local64_try_cmpxchg(&hwc->prev_count,
175 	local64_sub(delta, &hwc->period_left);
273 	struct hw_perf_event *hwc = &event->hw;
297 	if (hwc->sample_period) {
301 		if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
308 		hwc->sample_period &= ~0x0FULL;
309 		if (!hwc->sample_period)
310 			hwc->sample_period = 0x10;
315 		hwc->sample_period = event->attr.sample_period;
318 	if (!hwc->sample_period)
322 	 * If we modify hwc->sample_period, we also need to update
323 	 * hwc->last_period and hwc->period_left.
325 	hwc->last_period = hwc->sample_period;
326 	local64_set(&hwc->period_left, hwc->sample_period);
328 	hwc->config_base = perf_ibs->msr;
329 	hwc->config = config;
335 			       struct hw_perf_event *hwc, u64 *period)
340 	overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
341 	local64_set(&hwc->prev_count, 0);
392 					 struct hw_perf_event *hwc, u64 config)
394 	u64 tmp = hwc->config | config;
397 		wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
399 	wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
410 					  struct hw_perf_event *hwc, u64 config)
414 		wrmsrl(hwc->config_base, config);
416 	wrmsrl(hwc->config_base, config);
427 	struct hw_perf_event *hwc = &event->hw;
432 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
435 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
436 	hwc->state = 0;
438 	perf_ibs_set_period(perf_ibs, hwc, &period);
451 	perf_ibs_enable_event(perf_ibs, hwc, config);
458 	struct hw_perf_event *hwc = &event->hw;
469 	if (!stopping && (hwc->state & PERF_HES_UPTODATE))
472 	rdmsrl(hwc->config_base, config);
482 		perf_ibs_disable_event(perf_ibs, hwc, config);
493 		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
494 		hwc->state |= PERF_HES_STOPPED;
497 	if (hwc->state & PERF_HES_UPTODATE)
507 	hwc->state |= PERF_HES_UPTODATE;
1026 	struct hw_perf_event *hwc;
1052 	hwc = &event->hw;
1053 	msr = hwc->config_base;
1061 	perf_sample_data_init(&data, 0, hwc->last_period);
1062 	if (!perf_ibs_set_period(perf_ibs, hwc, &period))
1150 		perf_ibs_enable_event(perf_ibs, hwc, new_config);