cpu/sh4a/clock-sh7343.c

102 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
112 	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
143 	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
175 	[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
176 	[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
177 	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
178 	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
179 	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
180 	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
181 	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
182 	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
196 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),