drivers/pci/pci-sh7780.c

94 	struct pci_channel *hose = dev_id;
100 	addr = __raw_readl(hose->reg_base + SH4_PCIALR);
105 	status = __raw_readw(hose->reg_base + PCI_STATUS);
111 		cmd = pcibios_handle_status_errors(addr, status, hose);
113 			__raw_writew(cmd, hose->reg_base + PCI_STATUS);
119 	status = __raw_readl(hose->reg_base + SH4_PCIAINT);
127 	__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
132 	status = __raw_readl(hose->reg_base + SH4_PCIINT);
140 	__raw_writel(cmd, hose->reg_base + SH4_PCIINT);
147 	struct pci_channel *hose = dev_id;
154 	__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
158 	hose->serr_timer.expires = jiffies + HZ;
159 	add_timer(&hose->serr_timer);
164 static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
169 	__raw_writel(0, hose->reg_base + SH4_PCIAINT);
177 		     PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
179 	ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, 0,
180 			  "PCI SERR interrupt", hose);
192 	ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
193 			  "PCI ERR interrupt", hose);
195 		free_irq(hose->serr_irq, hose);
202 		     SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
210 		     SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
215 static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
217 	free_irq(hose->err_irq, hose);
218 	free_irq(hose->serr_irq, hose);
221 static void __init sh7780_pci66_init(struct pci_channel *hose)
225 	if (!pci_is_66mhz_capable(hose, 0, 0))
229 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);
231 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);
234 	tmp = __raw_readw(hose->reg_base + PCI_STATUS);
236 	__raw_writew(tmp, hose->reg_base + PCI_STATUS);
239 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);
241 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);