drivers/dma/dma-sh.c

39 static unsigned long dma_find_base(unsigned int chan)
44 	if (chan >= SH_DMAC_NR_MD_CH)
51 static unsigned long dma_base_addr(unsigned int chan)
53 	unsigned long base = dma_find_base(chan);
55 	chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ;
58 	if (chan >= DMAOR)
61 	return base + chan;
65 static inline unsigned int get_dmte_irq(unsigned int chan)
67 	return chan >= 6 ? DMTE6_IRQ : DMTE0_IRQ;
87 static inline unsigned int get_dmte_irq(unsigned int chan)
89 	return dmte_irq_map[chan];
103 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
105 	u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
120 	struct dma_channel *chan = dev_id;
123 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
129 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
131 	wake_up(&chan->wait_queue);
136 static int sh_dmac_request_dma(struct dma_channel *chan)
138 	if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
141 	return request_irq(get_dmte_irq(chan->chan), dma_tei, IRQF_SHARED,
142 			   chan->dev_id, chan);
145 static void sh_dmac_free_dma(struct dma_channel *chan)
147 	free_irq(get_dmte_irq(chan->chan), chan);
151 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
158 		chan->flags |= DMA_TEI_CAPABLE;
160 		chan->flags &= ~DMA_TEI_CAPABLE;
163 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
165 	chan->flags |= DMA_CONFIGURED;
169 static void sh_dmac_enable_dma(struct dma_channel *chan)
174 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
177 	if (chan->flags & DMA_TEI_CAPABLE)
180 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
182 	if (chan->flags & DMA_TEI_CAPABLE) {
183 		irq = get_dmte_irq(chan->chan);
188 static void sh_dmac_disable_dma(struct dma_channel *chan)
193 	if (chan->flags & DMA_TEI_CAPABLE) {
194 		irq = get_dmte_irq(chan->chan);
198 	chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
200 	__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
203 static int sh_dmac_xfer_dma(struct dma_channel *chan)
209 	if (unlikely(!(chan->flags & DMA_CONFIGURED)))
210 		sh_dmac_configure_channel(chan, 0);
212 	sh_dmac_disable_dma(chan);
229 	if (chan->sar || (mach_is_dreamcast() &&
230 			  chan->chan == PVR2_CASCADE_CHAN))
231 		__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
232 	if (chan->dar || (mach_is_dreamcast() &&
233 			  chan->chan == PVR2_CASCADE_CHAN))
234 		__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
236 	__raw_writel(chan->count >> calc_xmit_shift(chan),
237 		(dma_base_addr(chan->chan) + TCR));
239 	sh_dmac_enable_dma(chan);
244 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
246 	if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE))
249 	return __raw_readl(dma_base_addr(chan->chan) + TCR)
250 		 << calc_xmit_shift(chan);