riscv/kvm/vcpu_onereg.c

197 	unsigned long reg_val;
204 		reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
209 		reg_val = riscv_cbom_block_size;
214 		reg_val = riscv_cboz_block_size;
217 		reg_val = vcpu->arch.mvendorid;
220 		reg_val = vcpu->arch.marchid;
223 		reg_val = vcpu->arch.mimpid;
226 		reg_val = satp_mode >> SATP_MODE_SHIFT;
232 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
246 	unsigned long i, isa_ext, reg_val;
251 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
260 		if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
264 		 * Return early (i.e. do nothing) if reg_val is the same
267 		if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK))
275 					reg_val &= ~BIT(i);
279 					if (reg_val & BIT(i))
280 						reg_val &= ~BIT(i);
282 					if (!(reg_val & BIT(i)))
283 						reg_val |= BIT(i);
285 			reg_val &= riscv_isa_extension_base(NULL);
287 			reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
288 				  (reg_val & KVM_RISCV_BASE_ISA_MASK);
289 			vcpu->arch.isa[0] = reg_val;
298 		if (reg_val != riscv_cbom_block_size)
304 		if (reg_val != riscv_cboz_block_size)
308 		if (reg_val == vcpu->arch.mvendorid)
311 			vcpu->arch.mvendorid = reg_val;
316 		if (reg_val == vcpu->arch.marchid)
319 			vcpu->arch.marchid = reg_val;
324 		if (reg_val == vcpu->arch.mimpid)
327 			vcpu->arch.mimpid = reg_val;
332 		if (reg_val != (satp_mode >> SATP_MODE_SHIFT))
351 	unsigned long reg_val;
359 		reg_val = cntx->sepc;
362 		reg_val = ((unsigned long *)cntx)[reg_num];
364 		reg_val = (cntx->sstatus & SR_SPP) ?
369 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
384 	unsigned long reg_val;
391 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
395 		cntx->sepc = reg_val;
398 		((unsigned long *)cntx)[reg_num] = reg_val;
400 		if (reg_val == KVM_RISCV_MODE_S)
431 					  unsigned long reg_val)
439 		reg_val &= VSIP_VALID_MASK;
440 		reg_val <<= VSIP_TO_HVIP_SHIFT;
443 	((unsigned long *)csr)[reg_num] = reg_val;
453 						   unsigned long reg_val)
461 	((unsigned long *)csr)[reg_num] = reg_val;
488 	unsigned long reg_val, reg_subtype;
497 		rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);
500 		rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);
506 							      &reg_val);
515 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
530 	unsigned long reg_val, reg_subtype;
535 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
542 		rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);
545 		rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);
551 							      reg_val);
565 					 unsigned long *reg_val)
577 	*reg_val = 0;
579 		*reg_val = 1; /* Mark the given extension as available */
586 					 unsigned long reg_val)
598 	if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa))
606 		if (reg_val == 1 &&
609 		else if (!reg_val &&
624 					unsigned long *reg_val)
639 			*reg_val |= KVM_REG_RISCV_ISA_MULTI_MASK(ext_id);
647 					unsigned long reg_val, bool enable)
654 	for_each_set_bit(i, &reg_val, BITS_PER_LONG) {
674 	unsigned long reg_val, reg_subtype;
682 	reg_val = 0;
685 		rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, &reg_val);
689 		rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, &reg_val);
691 			reg_val = ~reg_val;
699 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
713 	unsigned long reg_val, reg_subtype;
721 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
726 		return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val);
728 		return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true);
730 		return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false);