riscv/kernel/traps_misaligned.c

136 #define REG_PTR(insn, pos, regs)	\
137 	(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
141 #define GET_RS1(insn, regs)		(*REG_PTR(insn, SH_RS1, regs))
142 #define GET_RS2(insn, regs)		(*REG_PTR(insn, SH_RS2, regs))
143 #define GET_RS1S(insn, regs)		(*REG_PTR(RVC_RS1S(insn), 0, regs))
144 #define GET_RS2S(insn, regs)		(*REG_PTR(RVC_RS2S(insn), 0, regs))
145 #define GET_RS2C(insn, regs)		(*REG_PTR(insn, SH_RS2C, regs))
146 #define GET_SP(regs)			(*REG_PTR(2, 0, regs))
147 #define SET_RD(insn, regs, val)		(*REG_PTR(insn, SH_RD, regs) = (val))
164 static int set_f32_rd(unsigned long insn, struct pt_regs *regs,
170 	regs->status |= SR_FS_DIRTY;
177 static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)
188 	regs->status |= SR_FS_DIRTY;
197 		      struct pt_regs *regs)
203 	regs->status |= SR_FS_DIRTY;
212 				struct pt_regs *regs)
218 	regs->status |= SR_FS_DIRTY;
228 				struct pt_regs *regs)
234 	regs->status |= SR_FS_DIRTY;
240 static void set_f32_rd(unsigned long insn, struct pt_regs *regs,
243 static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {}
246 				struct pt_regs *regs)
252 				struct pt_regs *regs)
259 #define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs))
260 #define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs))
261 #define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))
263 #define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs))
264 #define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs))
265 #define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))
267 #define __read_insn(regs, insn, insn_addr, type)	\
271 	if (user_mode(regs)) {				\
281 static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn)
288 		if (__read_insn(regs, insn, epc, u16))
300 		if (__read_insn(regs, tmp, epc, u16))
306 		if (__read_insn(regs, insn, epc, u32))
330 int handle_misaligned_load(struct pt_regs *regs)
333 	unsigned long epc = regs->epc;
335 	unsigned long addr = regs->badaddr;
338 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
347 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))
350 	if (get_insn(regs, epc, &insn))
353 	regs->epc = 0;
411 		regs->epc = epc;
419 	if (user_mode(regs)) {
427 		SET_RD(insn, regs, val.data_ulong << shift >> shift);
429 		set_f64_rd(insn, regs, val.data_u64);
431 		set_f32_rd(insn, regs, val.data_ulong);
433 	regs->epc = epc + INSN_LEN(insn);
438 int handle_misaligned_store(struct pt_regs *regs)
441 	unsigned long epc = regs->epc;
443 	unsigned long addr = regs->badaddr;
446 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
451 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))
454 	if (get_insn(regs, epc, &insn))
457 	regs->epc = 0;
459 	val.data_ulong = GET_RS2(insn, regs);
470 		val.data_u64 = GET_F64_RS2(insn, regs);
474 		val.data_ulong = GET_F32_RS2(insn, regs);
480 		val.data_ulong = GET_RS2S(insn, regs);
483 		val.data_ulong = GET_RS2C(insn, regs);
487 		val.data_ulong = GET_RS2S(insn, regs);
490 		val.data_ulong = GET_RS2C(insn, regs);
494 		val.data_u64 = GET_F64_RS2S(insn, regs);
498 		val.data_u64 = GET_F64_RS2C(insn, regs);
503 		val.data_ulong = GET_F32_RS2S(insn, regs);
507 		val.data_ulong = GET_F32_RS2C(insn, regs);
510 		regs->epc = epc;
517 	if (user_mode(regs)) {
524 	regs->epc = epc + INSN_LEN(insn);