powerpc/sysdev/fsl_pci.c

17 #include <linux/pci.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
81 		struct ccsr_pci __iomem *pci = hose->private_data;
83 		val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
145 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
168 		out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
169 		out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
170 		out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
171 		out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
198 /* atmu setup for fsl pci/pcie controller */
201 	struct ccsr_pci __iomem *pci = hose->private_data;
235 		if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
244 		out_be32(&pci->pow[i].powar, 0);
248 			out_be32(&pci->piw[i].piwar, 0);
261 		n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
280 			out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
281 			out_be32(&pci->pow[j].potear, 0);
282 			out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
284 			out_be32(&pci->pow[j].powar, 0x80088000
290 	/* convert to pci address space */
367 			out_be32(&pci->piw[win_idx].pitar,  0x00000000);
368 			out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
369 			out_be32(&pci->piw[win_idx].piwar,  piwar);
393 				out_be32(&pci->piw[win_idx].pitar,  0x00000000);
394 				out_be32(&pci->piw[win_idx].piwbear,
396 				out_be32(&pci->piw[win_idx].piwbar,
398 				out_be32(&pci->piw[win_idx].piwar,  piwar);
414 			out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
415 			out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
416 			out_be32(&pci->piw[win_idx].piwar,
429 				out_be32(&pci->piw[win_idx].pitar,
431 				out_be32(&pci->piw[win_idx].piwbar,
433 				out_be32(&pci->piw[win_idx].piwar, piwar);
531 	struct ccsr_pci __iomem *pci;
546 		printk(KERN_WARNING "Can't get pci register base!");
569 	pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
576 	if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
591 		    !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
604 		if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
830 		printk(KERN_WARNING "Can't get pci register base!\n");
838 			"No pci config register base in dev tree, "
1100 	{ .compatible = "fsl,mpc8540-pci", },
1102 	{ .compatible = "fsl,mpc8610-pci", },
1171 	struct ccsr_pci __iomem *pci = hose->private_data;
1174 	dr = in_be32(&pci->pex_pme_mes_dr);
1178 	out_be32(&pci->pex_pme_mes_dr, dr);
1185 	struct ccsr_pci __iomem *pci;
1217 	pci = hose->private_data;
1220 	clrbits32(&pci->pex_pme_mes_disr,
1223 	out_be32(&pci->pex_pme_mes_ier, 0);
1224 	setbits32(&pci->pex_pme_mes_ier,
1237 	struct ccsr_pci __iomem *pci = hose->private_data;
1242 	setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1246 		dr = in_be32(&pci->pex_pme_mes_dr);
1248 			out_be32(&pci->pex_pme_mes_dr, dr);
1273 	struct ccsr_pci __iomem *pci = hose->private_data;
1278 	setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1282 		dr = in_be32(&pci->pex_pme_mes_dr);
1284 			out_be32(&pci->pex_pme_mes_dr, dr);
1323 						   "mpc85xx-pci-edac",
1352 		.name = "fsl-pci",