platforms/powernv/pci-sriov.c

143 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
145 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
155 	pdev->dev.archdata.iov_data = iov;
159 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
163 			dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",
168 		vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
189 				pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",
202 		pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);
204 		pci_dbg(pdev, "                       %pR\n", res);
206 		pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
217 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
222 	pdev->dev.archdata.iov_data = NULL;
226 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
228 	if (pdev->is_virtfn) {
229 		struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
232 		 * VF PEs are single-device PEs so their pdev pointer needs to
233 		 * be set. The pdev doesn't exist when the PE is allocated (in
236 		pe->pdev = pdev;
238 	} else if (pdev->is_physfn) {
243 		pnv_pci_ioda_fixup_iov_resources(pdev);
247 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
250 	resource_size_t align = pci_iov_resource_size(pdev, resno);
251 	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
252 	struct pnv_iov_data *iov = pnv_iov_get(pdev);
284 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
290 	phb = pci_bus_to_pnvhb(pdev->bus);
291 	iov = pnv_iov_get(pdev);
415 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
426 	phb = pci_bus_to_pnvhb(pdev->bus);
427 	iov = pnv_iov_get(pdev);
430 		res = &pdev->resource[i + PCI_IOV_RESOURCES];
451 		size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i);
471 	pnv_pci_vf_release_m64(pdev, num_vfs);
475 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
480 	phb = pci_bus_to_pnvhb(pdev->bus);
482 	if (!pdev->is_physfn)
487 		if (pe->parent_dev != pdev)
591 static void pnv_pci_sriov_disable(struct pci_dev *pdev)
596 	iov = pnv_iov_get(pdev);
604 	pnv_ioda_release_vf_PE(pdev);
608 		pnv_pci_vf_resource_shift(pdev, -base_pe);
611 	pnv_pci_vf_release_m64(pdev, num_vfs);
614 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
623 	if (!pdev->is_physfn)
626 	phb = pci_bus_to_pnvhb(pdev->bus);
627 	pdn = pci_get_pdn(pdev);
628 	iov = pnv_iov_get(pdev);
632 		int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
633 		int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
640 		pe->parent_dev = pdev;
646 			pci_domain_nr(pdev->bus), pdev->bus->number,
652 			pe->pdev = NULL;
674 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
682 	phb = pci_bus_to_pnvhb(pdev->bus);
683 	iov = pnv_iov_get(pdev);
693 		pci_err(pdev, "SR-IOV is not supported on this PHB\n");
698 		dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");
705 		pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
713 	ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
715 		dev_info(&pdev->dev, "Not enough M64 window resources\n");
725 		ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);
731 	pnv_ioda_setup_vf_PE(pdev, num_vfs);
736 	pnv_pci_vf_release_m64(pdev, num_vfs);
745 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
747 	pnv_pci_sriov_disable(pdev);
750 	remove_sriov_vf_pdns(pdev);
754 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
757 	add_sriov_vf_pdns(pdev);
759 	return pnv_pci_sriov_enable(pdev, num_vfs);